Si3452/3
28 Rev. 0.47
13 DET4 Analog I/O Connection for port 4 detection, classification, and transient surge protection. This
pin is tied to VOUT4.
14 SDA Digital I/O I
2
C data pin
15 GND34 Ground Ground supply for protection clamps. Short to AGND, GND12, DGND.
16 SCL Digital I/O I
2
C clock pin
17 NC No connect Do not connect (float).
18 DET3 Analog I/O Connection for port 3 detection and classification. See DET4 for detailed descrip-
tion.
19 VDD Supply +3.3V (±10%) isolated supply. Short to VDD pin 30.
20 VOUT3 Analog I/O Port 3 power FET switch output. When on, provides a low impedance path to
VEE3.
21 AD3 Digital I/O Chip address bit 3 pin, read after reset. Address set with defined resistor dividers.
Pin also used for internal communications. Short to AD3 pin 24.
22 VEE3 Supply Driver 3 VEE supply. Short to VEE, VEE1/2/4.
23 RST
Digital input Active low digital reset. Short to RST pin 38.
24 AD3 Digital I/O Chip address bit 3 pin, read after reset. Address set with a 10 k
pull-up or pull-
down resistor. Also used for internal communications. Short to AD3 pin 21.
25 AD2 Digital I/O Chip address bit 2 pin, read after reset. Address set with a 10 k
pull-up or pull-
down resistor. Also used for internal communications. Short to AD2 pin 26.
26 AD2 Digital I/O Chip address bit 2 pin, read after reset. Address set with a 10 k
pull-up or pull-
down resistor. Also used for internal communications. Short to AD2 pin 25.
27 AD1 Digital I/O Chip address bit 1 pin, read after reset. Address set with a 10 k
pull-up or pull-
down resistor. Also used for internal communications. Short to AD1 pin 36.
28 AD0 Digital I/O Chip address bit 0 pin, read after reset. Address set with a 10 k
pull-up or pull-
down resistor. Also used for internal communications. Short to AD0 pin 34.
29 DGND Ground Digital ground reference. Short to AGND, GND12/34
30 VDD Supply +3.3 V isolated supply. Short to VDD pin 19.
31 VEE2 Supply Driver 2 VEE supply. Short to VEE, VEE1/3/4.
32 VOUT2 Analog I/O Port 2 power FET switch output. When on, provides a low impedance path to
VEE2.
33 DET2 Analog I/O Connection for port 2 detection and classification. See DET4 for detailed descrip-
tion.
34 AD0 Digital I/O Chip address bit 0 pin. See description for- and short to AD0 pin 28.
35 GND12 Ground Ground supply for protection clamps. Short to AGND, GND34, DGND.
36 AD1 Digital I/O Chip address bit 1 pin. See description for- and short to AD1 pin 27.
Table 25. Si3452/3 Pin Descriptions (Continued)
Pin # Name Type Description
Si3452/3
Rev. 0.47 29
37 DET1 Analog I/O Connection for port 1 detection and classification. See DET4 for detailed descrip-
tion.
38 RST
Digital input Active low digital reset. Short to RST pin 23.
39 VOUT1 Analog I/O Port 1 power FET switch output. When on, provides a low impedance path to
VEE1.
40 INT
Digital output Active low interrupt output pin.
Table 25. Si3452/3 Pin Descriptions (Continued)
Pin # Name Type Description
Si3452/3
30 Rev. 0.47
10. Package Outline: 40-Pin QFN
The Si3452/3 is packaged in an industry-standard, RoHS compliant 6 x 6 mm
2
, 40-pin QFN package.
Figure 7. 40-Pin QFN Mechanical Diagram
Table 26. Package Diagram Dimensions
Dimension Min Nom Max
A 0.80 0.85 0.90
A1 0.00 0.02 0.05
b 0.18 0.25 0.30
D 6.00 BSC.
D2 3.95 4.10 4.25
e 0.50 BSC.
E 6.00 BSC.
E2 3.95 4.10 4.25
L 0.30 0.40 0.50
aaa 0.10
bbb 0.10
ccc 0.08
ddd 0.10
eee 0.05
Notes:
1.
All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, Variation VJJD-2
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.

SI3452-B01-IM

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Hot Swap Voltage Controllers Quad PoE/PoE+ PSE port controller (dV/dt disconnect) - industrial temp
Lifecycle:
New from this manufacturer.
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