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M25P80-VMW6

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52
M25P80 Operating features
13/52
4.4 Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is enabled, and in the Active Power mode.
When Chip Select (S
) is High, the device is disabled, but could remain in the Active Power
mode until all internal cycles have completed (Program, Erase, Write Status Register). The
device then goes in to the Standby Power mode. The device consumption drops to I
CC1
.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep
Power-down mode (DP) instruction) is executed. The device consumption drops further to
I
CC2
. The device remains in this mode until another specific instruction (the Release from
Deep Power-down mode and Read Electronic Signature (RES) instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This
can be used as an extra software protection mechanism, when the device is not in active
use, to protect the device from inadvertent Write, Program or Erase instructions.
4.5 Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. For a detailed description of the Status Register bits,
see Section 6.4: Read Status Register (RDSR).
4.6 Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P80 boasts the following data protection mechanisms:
● Power-On Reset and an internal timer (t
PUW
) can provide protection against
inadvertent changes while the power supply is outside the operating specification.
● Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
● All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction completion
– Page Program (PP) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
● The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as
read-only. This is the Software Protected Mode (SPM).
● The Write Protect (W) signal allows the Block Protect (BP2, BP1, BP0) bits and Status
Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected
Mode (HPM).
● In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection from inadvertent Write, Program and Erase instructions, as all
instructions are ignored except one particular instruction (the Release from Deep
Power-down instruction).
Operating features M25P80
14/52
4.7 Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence. However, taking this signal Low does not terminate any
Write Status Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (S
) Low.
The Hold condition starts on the falling edge of the Hold (HOLD
) signal, provided that this
coincides with Serial Clock (C) being Low (as shown in Figure 5).
The Hold condition ends on the rising edge of the Hold (HOLD
) signal, provided that this
coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes
Low. (This is shown in Figure 5).
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
Normally, the device is kept selected, with Chip Select (S
) driven Low, for the whole duration
of the Hold condition. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the Hold condition.
If Chip Select (S
) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD
) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the Hold condition.
Table 2. Protected area sizes
Status Register
content
Memory content
BP2
bit
BP1
bit
BP0
bit
Protected area Unprotected area
0 0 0 none All sectors
(1)
(sixteen sectors: 0 to 15)
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are
0.
0 0 1 Upper sixteenth (Sector 15)
Lower fifteen-sixteenths (fifteen sectors:
0 to 14)
0 1 0 Upper eighth (two sectors: 14 and 15)
Lower seven-eighths (fourteen sectors:
0 to 13)
0 1 1 Upper quarter (four sectors: 12 to 15)
Lower three-quarters (twelve sectors: 0
to 11)
1 0 0 Upper half (eight sectors: 8 to 15) Lower half (eight sectors: 0 to 7)
1 0 1 All sectors (sixteen sectors: 0 to 15) none
1 1 0 All sectors (sixteen sectors: 0 to 15) none
1 1 1 All sectors (sixteen sectors: 0 to 15) none
M25P80 Operating features
15/52
Figure 5. Hold condition activation
AI02029D
HOLD
C
Hold
Condition
(standard use)
Hold
Condition
(non-standard use)
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M25P80-VMW6

Mfr. #:
Buy M25P80-VMW6
Manufacturer:
STMicroelectronics
Description:
NOR Flash 3.0V 8M (1Mx8)
Lifecycle:
New from this manufacturer.
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