M25P80 Power-up and Power-down
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7 Power-up and Power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V
CC
) until V
CC
reaches the correct value:
● V
CC
(min) at Power-up, and then for a further delay of t
VSL
●
V
SS
at Power-down
A safe configuration is provided in Section 3: SPI modes.
To avoid data corruption and inadvertent write operations during Power-up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while V
CC
is less
than the POR threshold value, V
WI
– all operations are disabled, and the device does not
respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of
t
PUW
has elapsed after the moment that V
CC
rises above the V
WI
threshold. However, the
correct operation of the device is not guaranteed if, by this time, V
CC
is still below V
CC
(min).
No Write Status Register, Program or Erase instructions should be sent until the later of:
● t
PUW
after V
CC
passed the V
WI
threshold
● t
VSL
after V
CC
passed the V
CC
(min) level
These values are specified in Table 8.
If the delay, t
VSL
, has elapsed, after V
CC
has risen above V
CC
(min), the device can be
selected for READ instructions even if the t
PUW
delay is not yet fully elapsed.
At Power-up, the device is in the following state:
● The device is in the Standby mode (not the Deep Power-down mode).
● The Write Enable Latch (WEL) bit is reset.
● The Write In Progress (WIP) bit is reset.
Normal precautions must be taken for supply rail decoupling, to stabilize the V
CC
feed. Each
device in a system should have the V
CC
rail decoupled by a suitable capacitor close to the
package pins. (Generally, this capacitor is of the order of 100 nF).
At Power-down, when V
CC
drops from the operating voltage, to below the Power On Reset
(POR) threshold value, V
WI
, all operations are disabled and the device does not respond to
any instruction. (The designer needs to be aware that if a Power-down occurs while a Write,
Program or Erase cycle is in progress, some data corruption can result.)
