30. These parameters are measured from a command/address signal transition edge to its
respective clock (CK, CK#) signal crossing. The specification values are not affected by
the amount of clock jitter applied as the setup and hold times are relative to the clock
signal crossing that latches the command/address. These parameters should be met
whether clock jitter is present.
31. For these parameters, the DDR3 SDRAM device supports
t
nPARAM (nCK) = RU(
t
PARAM
[ns]/
t
CK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For exam-
ple, the device will support
t
nRP (nCK) = RU(
t
RP/
t
CK[AVG]) if all input clock jitter specifi-
cations are met. This means that for DDR3-800 6-6-6, of which
t
RP = 5ns, the device will
support
t
nRP = RU(
t
RP/
t
CK[AVG]) = 6 as long as the input clock jitter specifications are
met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are
valid even if six clocks are less than 15ns due to input clock jitter.
32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the in-
ternal PRECHARGE command until
t
RAS (MIN) has been satisfied.
33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for
t
WR.
34. The start of the write recovery time is defined as follows:
• For BL8 (fixed by MRS or OTF): Rising clock edge four clock cycles after WL
• For BC4 (OTF): Rising clock edge four clock cycles after WL
• For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL
35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in
High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in exces-
sive current, depending on bus activity.
36. The refresh period is 64ms when T
C
is less than or equal to 85°C. This equates to an aver-
age refresh rate of 7.8125µs. However, nine REFRESH commands should be asserted at
least once every 70.3µs. When T
C
is greater than 85°C, the refresh period is 32ms. When
T
C
is greater than 105°C, the refresh period is 16ms. When T
C
is greater than 115°C, the
refresh period is 8ms.
37. Although CKE is allowed to be registered LOW after a REFRESH command when
t
REFPDEN (MIN) is satisfied, there are cases where additional time such as
t
XPDLL (MIN)
is required.
38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to
turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT
reference load is shown in Figure 19: ODT Timing Reference Load in the data sheet. De-
signs that were created prior to JEDEC tightening the maximum limit from 9ns to 8.5ns
will be allowed to have a 9ns maximum.
39. Half-clock output parameters must be derated by the actual
t
ERR10per and
t
JITdty when
input clock jitter is present. This results in each parameter becoming larger. The parame-
ters
t
ADC (MIN) and
t
AOF (MIN) are each required to be derated by subtracting both
t
ERR10per (MAX) and
t
JITdty (MAX). The parameters
t
ADC (MAX) and
t
AOF (MAX) are
required to be derated by subtracting both
t
ERR10per (MAX) and
t
JITdty (MAX).
40. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT
turn-off time maximum is when the DRAM buffer is in High-Z. The ODT reference load is
shown in Figure 19: ODT Timing Reference Load in the data sheet. This output load is
used for ODT timings (Figure 26: Reference Output Load for AC Timing and Output Slew
Rate in the data sheet).
41. Pulse width of a input signal is defined as the width between the first crossing of
V
REF(DC)
and the consecutive crossing of V
REF(DC)
.
42. Should the clock rate be larger than
t
RFC (MIN), an AUTO REFRESH command should
have at least one NOP command between it and another AUTO REFRESH command. Ad-
ditionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should
be followed by a PRECHARGE ALL command.
1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Electrical Characteristics and AC Operating Conditions
09005aef86775d6d
1gb_aut_DDR3L_1_35v_addendum.pdf - Rev. C 2/17 EN
16
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