MT41K128M8DA-107 AIT:J TR Datasheet MT41K128M8DA-107 AIT:J TR, MT41K64M16TW-107 AAT:J, MT41K64M16TW-107 AAT:J TR | P4-P6

Utra-high Temperature

The Utra-high temperature (UT) device requires that the case temperature not exceed

–40°C or 125°C. JEDEC specifications require the refresh rate to double when T

exceeds

85°C; this also requires use of the high-temperature auto refresh option. When T

+85°C, the refresh rate must be increased to 2X, when T

> +105°C, the refresh rate must

be increased to 4X and when T

> +115°C, the refresh rate must be increased to 8X. Self-

refresh mode is not available for T

> +105°C. Additionally, ODT resistance and the in-

put/output impedance must be derated when T

is <0°C or >85°C.

General Notes

• The functionality and the timing specifications discussed in this data sheet are for the

DLL enable mode of operation (normal operation).

• Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ is to be

interpreted as any and all DQ collectively, unless specifically stated otherwise.

• The terms “DQS” and “CK” found throughout this data sheet are to be interpreted as

DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise.

• Complete functionality may be described throughout the document; any page or dia-

gram may have been simplified to convey a topic and may not be inclusive of all re-

quirements.

• Any specific requirement takes precedence over a general statement.

• Any functionality not specifically stated is considered undefined, illegal, and not sup-

ported, and can result in unknown operation.

• Row addressing is denoted as A[n:0]. For example, 1Gb: n = 12 (x16); 1Gb: n = 13 (x4,

x8); 2Gb: n = 13 (x16) and 2Gb: n = 14 (x4, x8); 4Gb: n = 14 (x16); and 4Gb: n = 15 (x4,

x8).

• Dynamic ODT has a special use case: when DDR3 devices are architected for use in a

single rank memory array, the ODT ball can be wired HIGH rather than routed. Refer

to the Dynamic ODT Special Use Case section.

• A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be

used, use the lower byte for data transfers and terminate the upper byte as noted:

– Connect UDQS to ground via 1kΩ* resistor.

– Connect UDQS# to V

via 1kΩ* resistor.

– Connect UDM to V

via 1kΩ* resistor.

– Connect DQ[15:8] individually to either V

, V

, or V

REF

via 1kΩ resistors,* or float

DQ[15:8].

*If ODT is used, 1kΩ resistor should be changed to 4x that of the selected ODT.

1Gb: x8, x16 Automotive DDR3L SDRAM Addendum

Functional Description

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1gb_aut_DDR3L_1_35v_addendum.pdf - Rev. C 2/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Electrical Specifications

Absolute Ratings

Stresses greater than those listed may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at these or any other condi-

tions outside those indicated in the operational sections of this specification is not im-

plied. Exposure to absolute maximum rating conditions for extended periods may ad-

versely affect reliability.

Table 3: Absolute Maximum Ratings

Symbol Parameter Min Max Unit Notes

supply voltage relative to V

–0.4 1.975 V 1

DDQ

supply voltage relative to V

SSQ

–0.4 1.975 V

, V

OUT

Voltage on any pin relative to V

–0.4 1.975 V

Operating case temperature – Commercial 0 95 °C 2, 3

Operating case temperature – Industrial –40 95 °C 2, 3

Operating case temperature – Automotive –40 105 °C 2, 3

Operating case temperature – Ultra-high –40 125 °C 2, 3

STG

Storage temperature –55 150 °C

Notes:

1. V

and V

DDQ

must be within 300mV of each other at all times, and V

REF

must not be

greater than 0.6 × V

DDQ

. When V

and V

DDQ

are <500mV, V

REF

can be ≤300mV.

2. MAX operating case temperature. T

is measured in the center of the package.

3. Device functionality is not guaranteed if the DRAM device exceeds the maximum T

dur-

ing operation.

4. Ultra-high temperature use based on automotive usage model. Please contact Micron

sales representative if you have questions.

Input/Output Capacitance

Table 4: DDR3L Input/Output Capacitance

Note 1 applies to the entire table;

Capacitance

Parameters Symbol

DDR3L-1866

Unit NotesMin Max

CK and CK# C

0.8 1.3 pF

ΔC: CK to CK# C

DCK

0.0 0.15 pF

Single-end I/O: DQ, DM C

1.4 2.1 pF 2

Differential I/O: DQS, DQS#, TDQS, TDQS# C

1.4 2.1 pF 3

ΔC: DQS to DQS#, TDQS, TDQS# C

DDQS

0.0 0.15 pF 3

ΔC: DQ to DQS C

DIO

–0.5 0.3 pF 4

Inputs (CTRL, CMD, ADDR) C

0.75 1.2 pF 5

ΔC: CTRL to CK C

DI_CTRL

–0.4 0.2 pF 6

ΔC: CMD_ADDR to CK C

DI_CMD_ADDR

–0.4 0.4 pF 7

1Gb: x8, x16 Automotive DDR3L SDRAM Addendum

Electrical Specifications

09005aef86775d6d

1gb_aut_DDR3L_1_35v_addendum.pdf - Rev. C 2/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 4: DDR3L Input/Output Capacitance (Continued)

Note 1 applies to the entire table;

Capacitance

Parameters Symbol

DDR3L-1866

Unit NotesMin Max

ZQ pin capacitance C

– 3.0 pF

Reset pin capacitance C

– 3.0 pF

Notes:

1. V

= 1.35V (1.283–1.45V), V

DDQ

= V

, V

REF

= V

, f = 100 MHz, T

= 25°C. V

OUT(DC)

= 0.5

× V

DDQ

, V

OUT

= 0.1V (peak-to-peak).

2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.

3. Includes TDQS, TDQS#. C

DDQS

is for DQS vs. DQS# and TDQS vs. TDQS# separately.

4. C

DIO

= C

IO(DQ)

- 0.5 × (C

IO(DQS)

+ C

IO(DQS#)

5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR =

A[n:0], BA[2:0].

6. C

DI_CTRL

= C

I(CTRL)

- 0.5 × (C

CK(CK)

+ C

CK(CK#)

7. C

DI_CMD_ADDR

= C

I(CMD_ADDR)

- 0.5 × (C

CK(CK)

+ C

CK(CK#)

Thermal Characteristics

Table 5: Thermal Characteristics

Parameter/Condition Value Units Symbol Notes

Operating case temperature –

Commercial

0 to +85 °C T

1, 2, 3

Operating case temperature –

Industrial

–40 to +95 °C T

1, 2, 3, 4

Operating case temperature –

Automotive

–40 to +105 °C T

1, 2, 3, 4

Operating case temperature –

Ultra-high

–40 to +125 °C T

1, 2, 3, 4, 6

Junction-to-case (TOP) 78-ball “DA” 10.1 °C/W ΘJC 5

96-ball “TW” 9.4

Notes:

1. MAX operating case temperature. T

is measured in the center of the package.

2. A thermal solution must be designed to ensure the DRAM device does not exceed the

maximum T

during operation.

3. Device functionality is not guaranteed if the DRAM device exceeds the maximum T

dur-

ing operation.

4. If T

exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9µs

interval refresh rate. The use of SRT or ASR must be enabled.

5. The thermal resistance data is based off of a number of samples from multiple lots and

should be viewed as a typical number.

6. Ultra-high temperature use based on automotive usage model. Please contact Micron

sales representative if you have questions.

1Gb: x8, x16 Automotive DDR3L SDRAM Addendum

Thermal Characteristics

09005aef86775d6d

1gb_aut_DDR3L_1_35v_addendum.pdf - Rev. C 2/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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MT41K128M8DA-107 AIT:J TR

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DRAM DDR3 1G 128MX8 FBGA

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