MT41K64M16TW-107 AAT:J Datasheet MT41K128M8DA-107 AIT:J TR, MT41K64M16TW-107 AAT:J, MT41K64M16TW-107 AAT:J TR | P1-P3

Addendum Automotive DDR3L SDRAM

MT41K128M8 – 16 Meg x 8 x 8 banks

MT41K64M16 – 8 Meg x 16 x 8 banks

Description

This addendum provides information to add Automo-

tive Ultra-high Temperature (AUT) option for the data

sheet. This addendum does not provide detailed infor-

mation about the device. Refer to the data sheet (1Gb:

x8, x16 Automotive DDR3L SDRAM, Rev. B 2/15 EN)

for a complete description of device functionality, op-

erating modes, and specifications for the same Micron

part number products. The 1.35V DDR3L SDRAM de-

vice is a low-voltage version of the 1.5V DDR3 SDRAM

device. Refer to the DDR3 (1.5V) SDRAM data sheet

specifications when running in 1.5V compatible

mode.

Features

• V

= V

DDQ

= 1.35V (1.283V to 1.45V)

• Backward compatible to V

= V

DDQ

= 1.5V ±0.075V

• Differential bidirectional data strobe

• 8n-bit prefetch architecture

• Differential clock inputs (CK, CK#)

• 8 internal banks

• Nominal and dynamic on-die termination (ODT)

for data, strobe, and mask signals

• Programmable CAS (READ) latency (CL)

• Programmable CAS additive latency (AL)

• Programmable CAS (WRITE) latency (CWL)

• Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

• Selectable BC4 or BL8 on-the-fly (OTF)

• Self refresh mode

• T

of –40°C to 125°C

– 64ms, 8192-cycle refresh at –40°C to 85°C

– 32ms at 85°C to 105°C

– 16ms at 105°C to 115°C

– 8ms at 115°C to 125°C

• Self refresh temperature (SRT)

• Automatic self refresh (ASR)

• Write leveling

• Multipurpose register

• Output driver calibration

• AEC-Q100

• PPAP submission

• 8D response time

Options

Marking

• Configuration

– 128 Meg x 8 128M8

– 64 Meg x 16 64M16

• FBGA package (Pb-free) – x8

– 78-ball FBGA (8mm x 10.5mm) DA

• FBGA package (Pb-free) – x16

– 96-ball FBGA (8mm x 14mm) TW

• Timing – cycle time

– 1.07ns @ CL = 13 (DDR3-1866) -107

• Product certification

– Automotive A

• Operating temperature

– Industrial (–40°C ≤ T

≤ +95°C) IT

– Automotive (–40°C ≤ T

≤ +105°C) AT

– Ultra-high (–40°C ≤ T

≤ +125°C)

• Revision :J

Notes:

1. Not all options listed can be combined to

define an offered product. Use the part

catalog search on http://www.micron.com

for available offerings.

2. The datasheet does not support ×4 mode

even though ×4 mode description exists in

the following sections.

3. The UT option use based on automotive us-

age model. Contact Micron sales represen-

tative for further information.

Table 1: Key Timing Parameters

Speed Grade Data Rate (MT/s) Target

RCD-

RP-CL

RCD (ns)

RP (ns) CL (ns)

-107 1866 13-13-13 13.91 13.91 13.91

1Gb: x8, x16 Automotive DDR3L SDRAM Addendum

Description

09005aef86775d6d

1gb_aut_DDR3L_1_35v_addendum.pdf - Rev. C 2/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

Table 2: Addressing

Parameter 128 Meg x 8 64 Meg x 16

Configuration 16 Meg x 8 x 8 banks 8 Meg x 16 x 8 banks

Refresh count 8K 8K

Row address 16K A[13:0] 8K A[12:0]

Bank address 8 BA[2:0] 8 BA[2:0]

Column address 1K A[9:0] 1K A[9:0]

Page Size 1KB 2KB

Figure 1: DDR3L Part Numbers

Package Mark

Example Part Number: MT41K64M16DA-107AAT:J

Configuration

128 Meg x 8

64 Meg x 16

128M8

64M16

Speed Grade

CK = 1.07ns, CL = 13

ConfigurationMT41K Package Speed

Revision

Revision:J

Temperature

Industrial temperature

{

78-ball FBGA, 8mm x 10.5mm

96-ball FBGA, 8mm x 14mm

Automotive temperature

Ultra-high temperature

Certification

Automotive

Mark

107

Mark

Note:

1. Not all options listed can be combined to define an offered product. Use the part catalog search on

http://www.micron.com for available offerings.

1Gb: x8, x16 Automotive DDR3L SDRAM Addendum

Description

09005aef86775d6d

1gb_aut_DDR3L_1_35v_addendum.pdf - Rev. C 2/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Functional Description

DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.

The double data rate architecture is an 8n-prefetch architecture with an interface de-

signed to transfer two data words per clock cycle at the I/O pins. A single read or write

operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-

cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-

half-clock-cycle data transfers at the I/O pins.

The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for

use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data

for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the

data strobes.

The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK

going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, com-

mand, and address signals are registered at every positive edge of CK. Input data is reg-

istered on the first rising edge of DQS after the WRITE preamble, and output data is ref-

erenced on the first rising edge of DQS after the READ preamble.

Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a se-

lected location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVATE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with

the ACTIVATE command are used to select the bank and row to be accessed. The ad-

dress bits registered coincident with the READ or WRITE commands are used to select

the bank and the starting column location for the burst access.

The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be

enabled to provide a self-timed row precharge that is initiated at the end of the burst

access.

As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM

allows for concurrent operation, thereby providing high bandwidth by hiding row pre-

charge and activation time.

A self refresh mode is provided, along with a power-saving, power-down mode.

Industrial Temperature

The industrial temperature (IT) device requires that the case temperature not exceed

–40°C or 95°C. JEDEC specifications require the refresh rate to double when T

exceeds

85°C; this also requires use of the high-temperature self refresh option. Additionally,

ODT resistance and the input/output impedance must be derated when T

is <0°C or

>85°C.

Automotive Temperature

The automotive temperature (AT) device requires that the case temperature not exceed

–40°C or 105°C. JEDEC specifications require the refresh rate to double when T

exceeds

85°C; this also requires use of the high-temperature self refresh option. Additionally,

ODT resistance and the input/output impedance must be derated when T

is <0°C or

>85°C.

1Gb: x8, x16 Automotive DDR3L SDRAM Addendum

Functional Description

09005aef86775d6d

1gb_aut_DDR3L_1_35v_addendum.pdf - Rev. C 2/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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MT41K64M16TW-107 AAT:J

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