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MT41K64M16TW-107 AAT:J

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
Table 7: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
Parameter Symbol
DDR3L-1866
Unit NotesMin Max
Data setup time to DQS,
DQS#
Base (specification) @
2 V/ns
t
DS
(AC130)
70 – ps 18, 19
V
REF
@ 2 V/ns 135 – ps 19, 20
Data hold time from DQS,
DQS#
Base (specification) @
2 V/ns
t
DH
(DC90)
75 – ps 18, 19
V
REF
@ 2 V/ns 110 – ps 19, 20
Minimum data pulse width
t
DIPW 320 – ps 41
DQ Output Timing
DQS, DQS# to DQ skew, per access
t
DQSQ – 85 ps
DQ output hold time from DQS, DQS#
t
QH 0.38 –
t
CK (AVG) 21
DQ Low-Z time from CK, CK#
t
LZDQ –390 195 ps 22, 23
DQ High-Z time from CK, CK#
t
HZDQ – 195 ps 22, 23
DQ Strobe Input Timing
DQS, DQS# rising to CK, CK# rising
t
DQSS –0.27 0.27 CK 25
DQS, DQS# differential input low pulse width
t
DQSL 0.45 0.55 CK
DQS, DQS# differential input high pulse width
t
DQSH 0.45 0.55 CK
DQS, DQS# falling setup to CK, CK# rising
t
DSS 0.18 – CK 25
DQS, DQS# falling hold from CK, CK# rising
t
DSH 0.18 – CK 25
DQS, DQS# differential WRITE preamble
t
WPRE 0.9 – CK
DQS, DQS# differential WRITE postamble
t
WPST 0.3 – CK
DQ Strobe Output Timing
DQS, DQS# rising to/from rising CK, CK#
t
DQSCK –195 195 ps 23
DQS, DQS# rising to/from rising CK, CK# when
DLL is disabled
t
DQSCK
(DLL_DIS)
1 10 ns 26
DQS, DQS# differential output high time
t
QSH 0.40 – CK 21
DQS, DQS# differential output low time
t
QSL 0.40 – CK 21
DQS, DQS# Low-Z time (RL - 1)
t
LZDQS –390 195 ps 22, 23
DQS, DQS# High-Z time (RL + BL/2)
t
HZDQS – 195 ps 22, 23
DQS, DQS# differential READ preamble
t
RPRE 0.9 Note 24 CK 23, 24
DQS, DQS# differential READ postamble
t
RPST 0.3 Note 27 CK 23, 27
Command and Address Timing
DLL locking time
t
DLLK 512 – CK 28
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
t
IS
(AC135)
65 – ps 29, 30, 44
V
REF
@ 1 V/ns 200 – ps 20, 30
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
t
IS
(AC125)
150 – ps 29, 30, 44
V
REF
@ 1 V/ns 275 – ps 20, 30
1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Electrical Characteristics and AC Operating Conditions
09005aef86775d6d
1gb_aut_DDR3L_1_35v_addendum.pdf - Rev. C 2/17 EN
10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Table 7: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
Parameter Symbol
DDR3L-1866
Unit NotesMin Max
CTRL, CMD, ADDR hold
from CK,CK#
Base (specification)
t
IH
(DC90)
110 – ps 29, 30
V
REF
@ 1 V/ns 200 – ps 20, 30
Minimum CTRL, CMD, ADDR pulse width
t
IPW 535 – ps 41
ACTIVATE to internal READ or WRITE delay
t
RCD See Speed Bin Tables for
t
RCD
ns 31
PRECHARGE command period
t
RP See Speed Bin Tables for
t
RP
ns 31
ACTIVATE-to-PRECHARGE command period
t
RAS See Speed Bin Tables for
t
RAS
ns 31, 32
ACTIVATE-to-ACTIVATE command period
t
RC See Speed Bin Tables for
t
RC
ns 31, 43
ACTIVATE-to-ACTIVATE
minimum command period
1KB page size
t
RRD MIN = greater of 4CK or
5ns
CK 31
2KB page size MIN = greater of 4CK or
6ns
CK 31
Four ACTIVATE
windows
1KB page size
t
FAW 27 – ns 31
2KB page size 35 – ns 31
Write recovery time
t
WR MIN = 15ns; MAX = N/A ns 31, 32, 33
Delay from start of internal WRITE transaction to
internal READ command
t
WTR MIN = greater of 4CK or
7.5ns; MAX = N/A
CK 31, 34
READ-to-PRECHARGE time
t
RTP MIN = greater of 4CK or
7.5ns; MAX = N/A
CK 31, 32
CAS#-to-CAS# command delay
t
CCD MIN = 4CK; MAX = N/A CK
Auto precharge write recovery + precharge time
t
DAL MIN = WR +
t
RP/
t
CK (AVG);
MAX = N/A
CK
MODE REGISTER SET command cycle time
t
MRD MIN = 4CK; MAX = N/A CK
MODE REGISTER SET command update delay
t
MOD MIN = greater of 12CK or
15ns; MAX = N/A
CK
MULTIPURPOSE REGISTER READ burst end to
mode register set for multipurpose register exit
t
MPRR MIN = 1CK; MAX = N/A CK
Calibration Timing
ZQCL command: Long cali-
bration time
POWER-UP and RE-
SET operation
t
ZQinit MAX = N/A
MIN = MAX(512nCK,
640ns)
CK
Normal operation
t
ZQoper MAX = N/A
MIN = MAX(256nCK,
320ns)
CK
ZQCS command: Short calibration time MAX = N/A
MIN = MAX(64nCK, 80ns)
t
ZQCS
CK
Initialization and Reset Timing
1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Electrical Characteristics and AC Operating Conditions
09005aef86775d6d
1gb_aut_DDR3L_1_35v_addendum.pdf - Rev. C 2/17 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Table 7: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
Parameter Symbol
DDR3L-1866
Unit NotesMin Max
Exit reset from CKE HIGH to a valid command
t
XPR MIN = greater of 5CK or
t
RFC + 10ns; MAX = N/A
CK
Begin power supply ramp to power supplies sta-
ble
t
VDDPR MIN = N/A; MAX = 200 ms
RESET# LOW to power supplies stable
t
RPS MIN = 0; MAX = 200 ms
RESET# LOW to I/O and R
TT
High-Z
t
IOZ MIN = N/A; MAX = 20 ns 35
Refresh Timing
REFRESH-to-ACTIVATE or REFRESH
command period
t
RFC – 1Gb MIN = 110; MAX = 70,200 ns
t
RFC – 2Gb MIN = 160; MAX = 70,200 ns
t
RFC – 4Gb MIN = 260; MAX = 70,200 ns
t
RFC – 8Gb MIN = 350; MAX = 70,200 ns
Maximum refresh
period
T
C
≤ 85°C – 64 (1X) ms 36
T
C
> 85°C 32 (2X) ms 36
T
C
> 105°C 16 (4X) ms 36
T
C
> 115°C 8 (8X) ms 36
Maximum average
periodic refresh
T
C
≤ 85°C
t
REFI 7.8 (64ms/8192) µs 36
T
C
> 85°C 3.9 (32ms/8192) µs 36
T
C
>105°C 1.95 (16ms/8192) µs 36
T
C
>115°C 0.977 (8ms/8192) µs 36
Self Refresh Timing
45
Exit self refresh to commands not requiring a
locked DLL
t
XS MIN = greater of 5CK or
t
RFC + 10ns; MAX = N/A
CK
Exit self refresh to commands requiring a
locked DLL
t
XSDLL MIN =
t
DLLK (MIN);
MAX = N/A
CK 28
Minimum CKE low pulse width for self refresh
entry to self refresh exit timing
t
CKESR MIN =
t
CKE (MIN) + CK;
MAX = N/A
CK
Valid clocks after self refresh entry or power-
down entry
t
CKSRE MIN = greater of 5CK or
10ns; MAX = N/A
CK
Valid clocks before self refresh exit,
power-down exit, or reset exit
t
CKSRX MIN = greater of 5CK or
10ns; MAX = N/A
CK
Power-Down Timing
CKE MIN pulse width
t
CKE (MIN) Greater of 3CK or 5ns CK
Command pass disable delay
t
CPDED MIN = 2;
MAX = N/A
CK
Power-down entry to power-down exit timing
t
PD MIN =
t
CKE (MIN);
MAX = 9 ×
t
REFI
CK
Begin power-down period prior to CKE
registered HIGH
t
ANPD WL - 1CK CK
1Gb: x8, x16 Automotive DDR3L SDRAM Addendum
Electrical Characteristics and AC Operating Conditions
09005aef86775d6d
1gb_aut_DDR3L_1_35v_addendum.pdf - Rev. C 2/17 EN
12
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

MT41K64M16TW-107 AAT:J

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Buy MT41K64M16TW-107 AAT:J
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Micron
Description:
DRAM DDR3 1G 64MX16 FBGA
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