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PIC18F24K20-E/SS

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
PIC18F24K20/25K20/44K20/45K20
DS80000425P-page 4 2008-2015 Microchip Technology Inc.
Silicon Errata Issues
1. Module: ECCP
Changing the CCP1M<3:0> bits of CCP1CON
may cause the CCPR1H and CCPR1L registers to
capture the value of Timer1.
Work around
Halt Timer1 before changing ECCP mode. Reload
Timer1 with desired value after ECCP is setup and
before Timer1 is restarted.
Affected Silicon Revisions
2. Module: ECCP
Changing direction in Full-Bridge mode does not
insert dead time between changing the active
drivers in common legs of the bridge.
Work around
None.
Affected Silicon Revisions
3. Module: MSSP SPI
When the SPI clock is configured for Timer2/2
(SSPCON1<3:0> = 0011), the first SPI high time
may be short.
Work around
Option 1: Ensure TMR2 value rolls over to zero
immediately before writing to SSPBUF.
Option 2: Turn Timer2 off and clear TMR2 before
writing SSPBUF. Enable TMR2 after
SSPBUF is written.
Affected Silicon Revisions
4. Module: MSSP I
2
C
Slew rate is slower than I
2
C specifications when
the SLRCON<2> bit is set.
Work around
Clear SLRCON<2> bit when using the I
2
C
peripheral.
Affected Silicon Revisions
5. Module: ADC
Offset error is 3 LSb typical, 7 LSb maximum,
including an acquisition time-dependent
component (~2 LSb).
Work around
The time dependent error is insignificant when the
time between conversions is less than 100 ms.
When the time since the previous conversion is
greater than 100 ms then take two ADC
conversions and discard the first.
Affected Silicon Revisions
6. Module: MSSP I
2
C
If a new address byte is received while the BF flag
is set, the SSPOV bit is properly set and an ACK is
not properly generated. If only the SSPOV bit is set
(BF flag was cleared) and a matching address is
clocked in, that received byte will be improperly
loaded into the SSPBUF register and an ACK will
be improperly generated.
Work around
None.
Affected Silicon Revisions
Note 1: This document summarizes all silicon
errata issues from all specified revisions
of silicon.
2: Shaded cells in this section indicate latest
silicon in production.
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
2008-2015 Microchip Technology Inc. DS80000425P-page 5
PIC18F24K20/25K20/44K20/45K20
7. Module: MSSP I
2
C
I
2
C Master mode is not functional (Rev. A4 only).
Work around
Use software to emulate Master mode.
Affected Silicon Revisions
8. Module: MSSP SPI
In SPI Master mode, when the CKE bit is cleared
and the SMP bit is set, the last bit of the incoming
data stream (bit 0) at the SDI pin will not be
sampled properly.
Work around
None.
Affected Silicon Revisions
9. Module: MSSP SPI
In SPI Master mode, when CKE bit is set, the
SSPBUF will reload the SSPSR output shift
register on every high-to-low transition of the SS
pin.
Work around
Avoid using the SS pin when the CKE bit is set and
the MSSP is configured for SPI Master mode.
Affected Silicon Revisions
10. Module: MSSP SPI
When SPI is enabled in Master mode with
CKE = 1 and CKP = 0, a 1/F
OSC wide pulse will
occur on the SCK pin.
Work around
Configure SCK pin as an input until after the MSSP
is setup.
Affected Silicon Revisions
11. Module: EUSART
In Synchronous Master mode, when the SPBRG is
set to an odd number, the duty cycle of the CK
output will be skewed by one baud clock count.
Work around
High values of SPBRG will minimize the effect of
this anomaly.
Affected Silicon Revisions
12. Module: EUSART
In Synchronous Master mode, when the SPBRG is
set to 3 and the TXREG is written while the
previous character is still in the TX shift register,
the LS bit of the TXREG character may be
corrupted during transmission.
Work around
When SPBRG is set to 3, wait until the TRMT bit of
the TXSTA register is set before loading TXREG
with the next character to be transmitted.
Affected Silicon Revisions
13. Module: EUSART
In Synchronous Master mode, if the SPBRG
register is equal to 0 when the TXEN bit is set, then
writing to TXREG will properly start transmission.
However, the clock will be improperly out of phase
with the data bits and the clock will not stop at the
end of the character transmission.
Work around
Set SPBRG register to non-zero value before
setting the TXEN bit.
Affected Silicon Revisions
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
X
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
PIC18F24K20/25K20/44K20/45K20
DS80000425P-page 6 2008-2015 Microchip Technology Inc.
14. Module: Internal Fixed Voltage Reference
(FVR)
The FVRST bit of the CVRCON2 register activates
prematurely (Rev. A4 and A7 only).
Work around
Wait an additional 20 µs after FVRST is sensed
high before using the fixed voltage reference.
Enable the FVR by setting the FVREN bit of the
CVRCON2 register before activating any
peripheral that automatically enables the FVR.
Peripherals that automatically enable the FVR
include the Brown-out Reset, the High/Low-
Voltage Detect, and the HFINTOSC.
Affected Silicon Revisions
15. Module: High Low Voltage Detect (HLVD)
The IVRST bit of the HLVDCON register activates
prematurely (Rev. A4 and A7 only).
Work around
Wait an additional 20 µs after IVRST is sensed
high before using the fixed voltage reference.
Enable the FVR by setting the FVREN bit of the
CVRCON2 register before activating any
peripheral that automatically enables the FVR.
Peripherals that automatically enable the FVR
include the Brown-out Reset, the High/Low-
Voltage Detect, and the HFINTOSC.
Affected Silicon Revisions
16. Module: BOR
An unexpected Brown-out Reset may occur when
the fixed voltage reference is inactive and BOR is
activated, thereby activating the fixed voltage ref-
erence simultaneously. This error is caused by a
premature FVRST stable flag (Rev. A4 and A7
only) and only affects Brown-out disable in Sleep
and software enabled BOR modes.
Work around
Enable the FVR by setting the FVREN bit of the
CVRCON2 register and then wait an additional 20
µs after FVRST is sensed high before enabling
BOR. Brown-out disable in Sleep mode with
automatic enable on wake-up cannot be used.
Affected Silicon Revisions
17. Module: System Clocks
HFINTOSC output frequency is 16 MHz ±3%,
25°C to 85°C.
Work around
None.
Affected Silicon Revisions
18. Module: POR/BOR
The POR rearm voltage may be below the low end
of the BOR range, causing unexpected code
execution below the BOR range.
Work around
Use external power monitor to hold the device in
Reset below 1.1V.
Affected Silicon Revisions
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

PIC18F24K20-E/SS

Mfr. #:
Buy PIC18F24K20-E/SS
Manufacturer:
Microchip Technology
Description:
8-bit Microcontrollers - MCU 16KB Flash 768B RAM 25 I/O 8B
Lifecycle:
New from this manufacturer.
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