2008-2015 Microchip Technology Inc. DS80000425P-page 9
PIC18F24K20/25K20/44K20/45K20
30. Module: ECCP
ECCP – In Full-Bridge mode when PR2 =
CCPR1L and DC1B[1:0] <>‘00’ and the direction
is changed, then the dead time before the modu-
lated output starts is compromised. The modulated
signal improperly starts immediately with the direc-
tion change and stays on for T
OSC *TMR2
Prescale * DC1B[1:0].
Work around
Avoid changing direction when the duty cycle is
within three Least Significant steps of 100% duty
cycle. Instead, clear the DC1B[1:0] bits before the
direction change and then set them to the desired
value after the direction change is complete.
Affected Silicon Revisions
31. Module: MSSP SPI
When the SPI clock is configured for Timer2/2
(SSPCON1<3:0> = 0011) and the CKE bit of the
SSPSTAT register is ‘1’, then when SSPBUF is
written, the SCK output is improperly immediately
driven to the non-Idle state together with the MSb
value of the SSPBUF. The duration at which SDO
and SCK remain at these levels may be shorter
than a full half-bit period. The remaining bits in the
byte are output properly.
Work around
None.
Affected Silicon Revisions
32. Module: MSSP SPI
In SPI Master mode, when the CKE bit of the
SSPSTAT register is cleared and the SMP bit of
the SSPSTAT register is set, then the last bit of the
incoming data stream (bit 0) at the SDI pin will not
be sampled properly.
Work around
None.
Affected Silicon Revisions
33. Module: MSSP SPI
In SPI Master mode, if the SSPBUF register is
written while a byte is actively being transmitted,
an extra clock pulse will be improperly generated
at the end of the transmission. Further writes to the
SSPBUF register will be inhibited although 8 or 9
clock pulses will be generated for each attempted
write. The WCON bit of the SSPCON register is
properly set indicating that a write collision
occurred. However, the write collision condition
can only be cleared by resetting the MSSP
module. Clear the MSSP by clearing the SSPEN
bit of the SSPCON1 register.
Work around
Use the SSPIF bit of the PIR1 register or the BF bit
of the SSPSTAT register to determine that the
transmission is complete before writing the
SSPBUF register. In the event that a write collision
does occur, use the slave select feature to
resynchronize the slave clock.
Affected Silicon Revisions
34. Module: MSSP I
2
C
In Master I
2
C Receive mode if a Stop condition
occurs in the middle of an address or data
reception, then the SCL clock stream will continue
endlessly and the RCEN bit of the SSPCON2
register will remain set improperly. If a Start
condition occurs after the improper Stop condition
then nine additional clocks will be generated
followed by the RCEN bit going low.
Work around
Use low-impedance pull-ups on the SDA line to
reduce the possibility of noise glitches which may
trigger an improper Stop event. Use a time-out
event timer to detect the unexpected Stop
condition and resulting stuck RCEN bit. Clear the
stuck RCEN bit by clearing the SSPEN bit of
SSPCON1.
Affected Silicon Revisions
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXXXXXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXXXXXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXXXXXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXXXXXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXXXXXXX
