ISL76321
11
FN7803.2
May 1, 2015
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may require the deserializer to be manually reset. A 10ms delay
after the 1.8V supply is powered up guarantees normal
operation.
Power Supply Bypassing and Layout
The serializer and deserializer functions rely on the stable
functioning of PLLs locked to local reference sources or locked to
an incoming signal. It is important that the various supplies
(VDD_P, VDD_AN, VDD_CDR, VDD_TX) be well bypassed over a
wide range of frequencies, from below the typical loop bandwidth
of the PLL to approaching the signal bit rate of the serial data. A
combination of different values of capacitors from 1000pF to
5µF or more with low ESR characteristics is generally required.
The parallel LVCMOS VDD_IO
supply is inherently less sensitive,
but since the RGB and SYNC/DATAEN signals can all swing on the
same clock edge, the current in these pins, and the
corresponding GND pins, can undergo substantial current flow
changes. Once again, a combination of different values of
capacitors over a wide range, with low ESR characteristics, is
desirable.
A set of arrangements of this type is shown in Figure 5
, where
each supply is bypassed with a ferrite-bead-based choke, and a
range of capacitors. A “choke” is preferable to an “inductor” in
this application, since a high-Q inductor will be likely to cause one
or more resonances with the shunt capacitors, potentially
causing problems at or near those frequencies, while a “lossy”
choke will reflect a high impedance over a wide frequency range.
The higher value capacitor, in particular, needs to be chosen
carefully, with special care regarding its ESR. Very good results
can be obtained with multilayer ceramic capacitors (available
from many suppliers) and generally in small outlines (such as the
1210 outline suggested in the schematic shown in Figure 5
),
which provide good bypass capabilities down to a few mΩ at
1MHz to 2MHz. Other capacitor technologies may also be
suitable (perhaps niobium oxide), but “classic” electrolytic
capacitors frequently have ESR values of above 1Ω, that nullify
any decoupling effect above the 1kHz to 10kHz frequency range.
Capacitors of 0.1µF offer low impedance in the 10MHz to 20MHz
region, and 1000pF capacitors in the 100MHz to 200MHz region.
In general, one of the lower value capacitors should be used at
each supply pin on the IC. Figure 5
shows the grounding of the
various capacitors to the pin corresponding to the supply pin.
Although all the ground supplies are tied together, the PCB layout
should be arranged to emulate this arrangement (at least for the
smaller value (high frequency) capacitors), as much as possible.
I
2
C Interface
The I
2
C interface allows access to internal registers used to
configure the SERDES and to obtain status information. A
serializer must be assigned a different address than its
deserializer counterpart if the side channel is used. The upper 5
bits are permanently set to 011 11 and the lower 2 bits
determined by pins as follows:
Thus, 4 SERDES can reside on the same bus. By convention,
when all address pins are tied low, the device address is referred
to as 0x78.
SCL and SDA are open drain to allow multiple devices to share
the bus. If not used, SCL and SDA should be tied to VDD_IO.
Side Channel Interface
The Side Channel is a mechanism for transferring data between
the two chips on each end of the link. This data is transferred
during video blanking so none of the video bandwidth is used. It
has three basic uses:
• Remote SERDES configuration
• Data exchanges between two processors
•Master Mode I
2
C commands to remote slaves
This interface allows the user to initialize registers, control and
monitor both SERDES chips from a single microcontroller which
can reside on either side of the serial link. This feature is used to
automatically transport the remote side SERDES chip’s status
back to a local register. The Side Channel needs to be enabled
(the default) for this to work. In the case where there is a
microcontroller on each side of the of the link, data can be
buffered and exchanged between the two. Up to 224 bytes can
be sent in each direction during each VSYNC active period.
01111I2CA1I2CA0R/W
FIGURE 5. POWER SUPPLY BYPASSING
10µF
10µF
10µF
10µF
10µF
10µF
120Ω
120Ω
120Ω
120Ω
120Ω
120Ω
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
