ISL76321
4
FN7803.2
May 1, 2015
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18 VHSYNCPOL CMOS input for HSYNC and VSYNC Polarity
1: HSYNC & VSYNC active low
0: HSYNC & VSYNC active high
19 VIDEO_TX CMOS input for video flow direction
1: Video serializer
0: Video deserializer
24, 23 SDA, SCL (Note 1
)I
2
C Interface Pins (I
2
C DATA, I
2
C CLK), weak internal pull-up
25, 26 I2CA[1:0] (Note 1
)I
2
C Device Address
27 MASTER I
2
C Master Mode
1: Master
0: Slave
12 RSTB/PDB CMOS input for Reset and Power-down. For normal operation, this pin should be driven high. When this
pin is taken low, the device will be reset. If this pin stays low, the device will be in PD mode.
10 STATUS CMOS output for Receiver Status:
1: Valid 8b/10b data received
0: No valid data detected
Note: serializer and deserializer switch roles during side-channel reverse traffic
28 REF_RES Analog bias setting resistor connection; use 3.16kΩ ±1% to ground
21 GND_P (Note 2
)PLL Ground
37, 48 GND_IO (Note 2
) Digital (Parallel and Control) Ground
35 GND_CDR (Note 2
) Analog (Serial) Data Recovery Ground
31 GND_TX (Note 2
) Analog (Serial) Output Ground
29 GND_AN (Note 2
) Analog Bias Ground
13 GND_CR (Note 2
) Core Logic Ground
14 VDD_CR Core Logic VDD
34 VDD_TX Analog (Serial) Output VDD
30 VDD_AN Analog Bias VDD
36 VDD_CDR Analog (Serial) Data Recovery VDD
1, 38 VDD_IO (Note 1
) Digital (Parallel and Control) VDD
22 VDD_P PLL VDD
11 TEST_EN Must be connected to ground
Exposed Pad PAD Must be connected to ground, not an electrical connection
NOTES:
1. Pins with the same name are internally connected together. However, this connection must NOT be used for connecting together external components
or features.
2. The various differently-named Ground pins are internally weakly connected. They must be tied together externally. The different names are provided
to assist in minimizing the current loops involved in bypassing the associated supply VDD pins. In particular, for ESD testing, they should be
considered a common connection.
Pin Descriptions (Continued)
PIN NUMBER PIN NAME
DESCRIPTION
SERIALIZER DESERIALIZER
ISL76321
5
FN7803.2
May 1, 2015
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Ordering Information
PART NUMBER
(Notes 3
, 4, 5)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL76321ARZ ISL76321 ARZ -40 to +105 48 Ld QFN L48.7x7C
NOTES:
3. Add “-T*” suffix for tape and reel. Please refer to TB347
for details on reel specifications.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL76321
. For more information on MSL please see techbrief TB363.
ISL76321
6
FN7803.2
May 1, 2015
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Absolute Maximum Ratings Thermal Information
Supply Voltage
VDD_P to GND_P, VDD_TX to GND_TX, VDD_IO to GND_IO . . -0.5V to 4.6V
VDD_CDR to GND_CDR, VDD_CR to GND_CR . . . . . . . . . . . . . . . . -0.5V to 2.5V
Between any pair of GND_P, GND_TX, GND_IO, GND_CDR,
GND_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.1V to 0.1V
3.3V Tolerant LVTTL/LVCMOS
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD_IO +0.3V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD_IO + 0.3V
Differential Output Current . . . . . . . . . . . . . . . . . . . . Short Circuit Protected
LVTTL/LVCMOS Outputs. . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected
ESD Rating
Human Body Model (Tested per JESD22-A114E)
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV
SERIOP/N
(All VDD Connected, all GND Connected) . . . . . . . . . . . . . . . . . . . . . . 8kV
Machine Model (Tested per JESD-A115-A) . . . . . . . . . . . . . . . . . . . . 200V
Charge Device Model (Tested per AEC-Q100-011-B) . . . . . . . . . . . 2000V
Latch-up (Tested per JESD-78B; Class2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA
JC
(°C/W)
QFN Package (Notes 6
, 7) . . . . . . . . . . . . . . 32 3.7
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
7. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR
= VDD_CR = 1.8V, VDD_IO = 3.3V
,
VDD_TX = VDD_P = VDD_AN
= 3.3V, T
A
= +25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling capacitor = 27nF. Boldface limits apply over the operating
temperature range, -40°C to +105°C.
PARAMETER SYMBOL CONDITIONS
MIN
(Note 10
)TYP
MAX
(Note 10)UNITS
POWER SUPPLY VOLTAGE
VDD_CDR, VDD_CR 1.7 1.8 1.9 V
VDD_TX, VDD_P, VDD_AN, VDD_IO 3.0 3.3 3.6 V
SERIALIZER POWER SUPPLY CURRENTS
Total 1.8V Supply Current PCLK_IN = 45MHz 62 80 mA
Total 3.3V Supply Current (Note 8
)4052 mA
DESERIALIZER POWER SUPPLY CURRENTS
Total 1.8V Supply Current PCLK_IN = 45MHz 66 76 mA
Total 3.3V Supply Current (Note 8
)5063 mA
POWER-DOWN SUPPLY CURRENT
Total 1.8V Power-Down Supply Current RSTB = GND 10 mA
Total 3.3V Power-Down Supply Current 0.5 mA
PARALLEL INTERFACE
High Level Input Voltage V
IH
2.0 V
Low Level Input Voltage V
IL
0.8 V
Input Leakage Current I
IN
-1 ±0.01 1 µA
High Level Output Voltage V
OH
I
OH
= -4.0mA, VDD_IO = 3.0V 2.6 V
Low Level Output Voltage V
OL
I
OL
= 4.0mA, VDD_IO = 3.6V 0.4 V
Output Short Circuit Current I
OSC
35 mA

ISL76321ARZ-T7A

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Serializers & Deserializers - Serdes 48L QFN 7X7(PUNCHED) T&R, Auto
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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