Data Sheet ADF4113HV
Rev. B | Page 3 of 20
SPECIFICATIONS
AV
DD
= DV
DD
= 3 V ± 10%, 5 V ± 10%; 13.5 V < V
P
≤ 16.5 V; AGND = DGND = CPGND = 0 V; R
SET
= 4.7 kΩ; dBm referred to 50 Ω;
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Operating temperature range for B version: −40°C to +85°C.
Table 1.
RF CHARACTERISTICS (3 V)
RF Input Sensitivity −15/0 −15/0 dBm min/max
For lower frequencies, ensure SR > 130 V/μs
Prescaler Output Frequency
2
RF Input Frequency 0.2/3.7 0.2/3.7 GHz min/max For lower frequencies, ensure SR > 130 V/µs
0.2/4.0 0.2/4.0 GHz min/max Input level = −5 dBm
Prescaler Output Frequency 200 200 MHz max
REF
CHARACTERISTICS
REF
Input Frequency 5/150 5/150 MHz min/max For f < 5 MHz, ensure SR > 100 V/µs
Reference Input Sensitivity
AV
DD
= 3.3 V, biased at AV
DD
/2
3
For f ≥ 10 MHz, AV
DD
= 5 V, biased at AV
DD
/2
3, 4
REF
Input Capacitance 10 10 pF max
REF
Input Current ±100 ±100 µA max
PHASE DETECTOR FREQUENCY 5 5 MHz max
I
Sink/Source R
= 4.7 kΩ
High Value 640 640 μA typ
Low Value 80 80 µA typ
I
Three-State Leakage Current 5 5 nA max
Sink and Source Current Matching 3 3 % typ 1 V ≤ V
≤ V
– 1 V
I
vs. V
1.5 1.5 % typ 1 V ≤ V
≤ V
– 1 V
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
/I
, Input Current ±1 ±1 µA max
C
, Input Capacitance 10 10 pF max
LOGIC OUTPUTS
V
, Output High Voltage DV
− 0.4 DV
− 0.4 V min I
= 500 µA
V
, Output Low Voltage 0.4 0.4 V max I
= 500 µA
POWER SUPPLIES
AV
2.7/5.5 2.7/5.5 V min/V max
I
5
(AI
+ DI
) 16 11 mA max 11 mA typical
I
0.25 0.25 mA max T
= 25°C
Low Power Sleep Mode 1 1 µA typ
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
−212 −212 dBc/Hz typ
1
The B chip specifications are given as typical values.
2
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
3
AC coupling ensures AV
DD
/2 bias.
4
Guaranteed by characterization.
5
T
A
= 25
o
C; AV
DD
= DV
DD
= 5.5 V; P = 16; RF
IN
= 900 MHz.
6
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PN
TOT
, and subtracting 20logN (where N is the N divider
value) and 10logf
PFD
: PN
SYNTH
= PN
TOT
− 10logf
PFD
− 20logN.