1. General description
The 74LV4020 is a low-voltage Si-gate CMOS device and is pin and function compatible
with the 74HC4020 and 74HCT4020.
The 74LV4020 is a 14-stage binary ripple counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and 12 fully buffered parallel outputs (Q0, and
Q3 to Q13).
The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all
counter stages and forces all outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
2. Features
■ Optimized for low-voltage applications: 1.0 V to 5.5 V
■ Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
■ Typical LOW-level output voltage (peak) or output ground bounce: V
OL(p)
< 0.8 V at
V
CC
= 3.3 V and T
amb
=25°C
■ Typical HIGH-level output voltage (valley) or output V
OH
undershoot: V
OH(v)
>2V at
V
CC
= 3.3 V and T
amb
=25°C
■ ESD protection:
◆ HBM EIA/JESD22-A114-C exceeds 2000 V
◆ MM EIA/JESD22-A115-A exceeds 200 V.
■ Multiple package options
■ Specified from −40 °C to +80 °C and from −40 °C to +125 °C.
3. Applications
■ Frequency dividing circuits
■ Time delay circuits
■ Control counters
74LV4020
14-stage binary ripple counter
Rev. 01 — 29 November 2005 Product data sheet
