74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 01 — 29 November 2005 4 of 20
Philips Semiconductors
74LV4020
14-stage binary ripple counter
7. Pinning information
7.1 Pinning
7.2 Pin description
Fig 5. Pin configuration DIP16, SO16, SSOP16 and TSSOP16
4020
Q11 V
CC
Q12 Q10
Q13 Q9
Q5 Q7
Q4 Q8
Q6 MR
Q3 CP
GND Q0
001aad721
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 3: Pin description
Symbol Pin Description
Q11 1 parallel output 11
Q12 2 parallel output 12
Q13 3 parallel output 13
Q5 4 parallel output 5
Q4 5 parallel output 4
Q6 6 parallel output 6
Q3 7 parallel output 3
GND 8 ground (0 V)
Q0 9 parallel output 0
CP 10 clock input (HIGH-to-LOW, edge-triggered)
MR 11 master reset input (active HIGH)
Q8 12 parallel output 8
Q7 13 parallel output 7
Q9 14 parallel output 9
Q10 15 parallel output 10
V
CC
16 supply voltage
74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 01 — 29 November 2005 5 of 20
Philips Semiconductors
74LV4020
14-stage binary ripple counter
8. Functional description
8.1 Function table
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
= LOW-to-HIGH clock transition;
= HIGH-to-LOW clock transition.
8.1.1 Timing diagram
Table 4: Function table
[1]
Input Output
CP MR Q0, Q3 to Q13
L no change
L count
XHL
Fig 6. Timing diagram
001aad726
1 2 4 8 16 32 64 128 256 512 1024 2048 4096
CP input
MR input
Q0
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
8192 16384
Q12
Q13
74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 01 — 29 November 2005 6 of 20
Philips Semiconductors
74LV4020
14-stage binary ripple counter
9. Limiting values
[1] Above T
amb
= 70 °C: P
tot
derates linearly with 12 mW/K.
[2] Above T
amb
= 70 °C: P
tot
derates linearly with 8 mW/K.
[3] Above T
amb
= 60 °C: P
tot
derates linearly with 5.5 mW/K.
10. Recommended operating conditions
[1] The static characteristics are guaranteed from V
CC
= 1.2 V to V
CC
= 5.5 V, but LV devices are guaranteed to
function down to V
CC
= 1.0 V (with input levels GND or V
CC
).
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7 V
I
IK
input clamping current V
I
< 0.5 V or V
I
> V
CC
+ 0.5 V - ±20 mA
I
OK
output clamping current V
O
< 0.5 V or
V
O
>V
CC
+ 0.5 V
- ±50 mA
I
O
output current V
O
= 0.5 V to V
CC
+ 0.5 V - ±25 mA
I
CC
quiescent supply current - 50 mA
I
GND
ground current - 50 mA
T
stg
storage temperature 65 +150 °C
P
tot
total power dissipation T
amb
= 40 °C to +125 °C
DIP16 package
[1]
- 750 mW
SO16 package
[2]
- 500 mW
SSOP16 and
TSSOP16 packages
[3]
- 400 mW
Table 6: Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
V
CC
supply voltage
[1]
1.0 3.3 5.5 V
V
I
input voltage 0 - V
CC
V
V
O
output voltage 0 - V
CC
V
T
amb
ambient temperature 40 - +125 °C
t/V input transition rise and
fall rate
V
CC
= 1.0 V to 2.0 V - - 500 ns/V
V
CC
= 2.0 V to 2.7 V - - 200 ns/V
V
CC
= 2.7 V to 3.6 V - - 100 ns/V
V
CC
= 3.6 V to 5.5 V - - 50 ns/V

74LV4020DB,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Counter ICs 3.3V 14-STAGE BIN
Lifecycle:
New from this manufacturer.
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