NCV7707, NCV7707B
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28
CONTROL_1 Register
Address: 01h
Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Access type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit name HS7.1 HS7.0 HS8.1 HS8.0 HS9 HS10 HS11
LS
ECFB
DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 ECEN 0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HS Outputs
OUT7,8
Control
HSx.1 HSx.0 Description Remark
0 0 default OUTx High impedance
If a driver is enabled by the control register AND the
corresponding PWM enable bit is set in CONTROL_3
register, the output is only activated if the
corresponding PWM input signal (PWM pin or internal
PWM signal) is high.
0 1
Output enabled, low
current mode (LED
mode)
1 0
Output enabled, high
current mode (bulb
mode)
1 1 OUTx High impedance
HS Outputs
OUT9−11
Control
HSx Description Remark
0 default OUTx High impedance
If a driver is enabled by the control register AND the
corresponding PWM enable bit is set in CONTROL_3
register, the output is only activated if the
corresponding PWM input signal (PWM pin or internal
PWM signal) is high.
1 OUTx enabled
ECFB
Pull−down
Output Control
LS ECFB Description Remark
0 default
Pull−down transistor
disabled (high
impedance)
The ECFB−pull−down transistor can only be activated
if the DAC output voltage is set to 0 V (DAC[5:0]=0). If
the PWM enable bit CONTROL_2.ECFB_PWM1 is
set, the output will only be activated when the PWM1
signal input is high.
1
Pull−down transistor
enabled
Electrochrom.
Mirror
Reference
Voltage
DAC[5:0] Description Remark
0 default
Reference voltage for
ECON/ECFB
differential amplifier
If bit CONTROL_2.FSR=0, the output voltage is
clamped to 1.2 V.
n
Electrochrom.
Mirror Enable
ECEN Description Remark
0 default
Electrochromic mirror
controller disabled
By enabling the electrochromic mirror controller
(ECEN=1), the output driver for the external pass
transistor (ECON) is enabled. In addition, OUT10 is
activated, regardless of the setting of
CONTROL_1.HS10.
1
Electrochromic mirror
controller enabled
NCV7707, NCV7707B
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29
CONTROL_2 Register
Address: 02h
Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Access type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit name OCR1 OCR2 OCR3 OCR4 OCR5 OCR6
OCR
ECFB
PWMI
OUT1
PWM1
OUT2
PWM1
OUT3
PWM1
OUT4
PWM1
OUT5
PWM2
OUT6
PWM1
ECFB
PWM1
FSR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Overcurrent
Recovery
OCRx Description Remark
0 default
Overcurrent Recovery
disabled
During an overcurrent event the overcurrent status bit
STATUS_0/2.OCx is set and the dedicated output is
switched off. (The global multi bit UOV_OC is set,
also). When the overcurrent recovery bit is enabled,
the output will be reactivated automatically after a
programmable delay time (CONTROL_3.OCRF).
1
Overcurrent Recovery
enabled
PWM Unit
PWMI Description Remark
0 default
Internal PWM unit
disabled
The device has three different PWM sources: external
pins PWM1, PWM2 and the internal PWM unit which
can be used to control the lamp drivers in an
additional way. PWMI selects the internal PWM unit.
1
Internal PWM unit
enabled
PWM1/2
Selection
OUTx PWM Description Remark
0 default PWMx not selected
For the half−bridge outputs it is possible to select the
PWM input pins PWM1 or PWM2. In this case the
dedicated output (selected in CONTROL_0 register) is
on if the PWM input signal is high. OUT5 is controlled
by PWM2, all other half−bridges are controlled by
PWM1.
1 PWMx selected
DAC Full−scale
Range Control
FSR Description Remark
0 default
Vout = 1.5 / 2^6 ·
DAC[5:0] clamped at
1.2 V
The default voltage at ECFB in electrochrome mode is
clamped at 1.2 V, when FSR=1 the maximum value is
1.5 V.
1
Vout = 1.5 / 2^6 ·
DAC[5:0]
NCV7707, NCV7707B
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30
CONTROL_3 Register
Address: 03h
Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Access Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit name OCR7 OCR8 OCR9 OCR10 OCR11
OUT7
PWM1
OUT8
PWM2
OUT9
PWM1
OUT10
PWM2
OUT11
PWM1
OCRF OVUVR IS3 IS2 IS1 IS0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Overcurrent
Recovery
OCRx Description Remark
0 default
Overcurrent Recovery
disabled
During an overcurrent event the overcurrent status bit
STATUS_0/2.OCx is set and the dedicated output is
switched off. (The global multi bit UOV_OC is set,
also). When the overcurrent recovery bit is enabled,
the output will be reactivated automatically after a
programmable delay time (CONTROL_3.OCRF).
1
Overcurrent Recovery
enabled
PWM1/2
Selection
OUTx PWM Description Remark
0 default PWMx not selected
For the HS outputs it is possible to select the PWM
input pins PWM1, PWM2 or internal PWMI unit
(OUT7−10 only). In this case the dedicated output
(selected in CONTROL_1 register) is on if the PWM
input signal is high. OUT8 and OUT10 are controlled
by PWM2, OUT7,9 and OUT11 are controlled by
PWM1.
1 PWMx selected
Overcurrent
Recovery
Frequency
Selection
OCRF Description Remark
0 default
Slow Overcurrent re-
covery mode
If the overcurrent recovery bit is set, the output will be
switched on automatically after a delay time. The
recovery behavior of OUT7,8 in bulb mode is not
affected by this bit.
1
Fast Overcurrent re-
covery mode
Over− /
Under−voltage
Recovery
OVUVR Description Remark
0 default
Over− and
undervoltage recovery
function enabled
If the OV/UV recovery is disabled by setting
OVUVR=1, the status register STATUS_2 bits VSOV
or VSUV have to be cleared after an OV/UV event.
1
No over− and
undervoltage recovery

NCV7707DQR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Motor / Motion / Ignition Controllers & Drivers DOOR-MODULE DVR-IC
Lifecycle:
New from this manufacturer.
Delivery:
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