DocID030317 Rev 2 7/18
L6494 Electrical characteristics
18
4 Electrical characteristics
Table 5. Electrical characteristics (V
CC
= 15 V; T
J
= +25 °C; PGND = SGND)
Symbol Pin Parameter Test condition Min. Typ. Max. Unit
Low-side section supply
V
CC_hys
VCC vs.
SGND
V
CC
UV hysteresis - 0.5 0.6 0.72 V
V
CC _thON
V
CC
UV turn ON threshold - 8.7 9.3 9.8 V
V
CC _thOFF
V
CC
UV turn OFF threshold - 8.2 8.7 9.2 V
I
QCCU
Undervoltage quiescent supply
current
V
CC
= SD = 7 V
IN = SGND
- 135 200 A
I
QCC
Quiescent current
V
CC
= 15 V
SD
= 5 V; IN = SGND
- 490 700 A
High-side floating section supply
(1)
V
BO_hys
BOOT vs.
OUT
V
BO
UV hysteresis - 0.48 0.6 0.7 V
V
BO_thON
V
BO
UV turn ON threshold - 8.0 8.6 9.1 V
V
BO_thOFF
V
BO
UV turn OFF threshold - 7.5 8.0 8.5 V
I
QBOU
Undervoltage V
BO
quiescent
current
V
BO
= SD = 7 V
IN = SGND
-2030A
I
QBO
V
BO
quiescent current
VBO = 15 V
SD = IN = 5 V
-90120A
I
LK
High-voltage leakage current V
hvg
= V
out
= V
boot
= 600 V - - 8 A
R
DS(on)
Bootstrap diode on-resistance
(2)
- - 175 -
Output driving buffers
I
SO
LVG, HVG
High/low-side source short-circuit
current
LVG/HVG ON
T
J
= 25 °C
1.6 2 - A
Full temperature range
(3)
1.25 - - A
I
SI
High/low-side sink short-circuit
current
LVG/HVG ON
T
J
= 25 °C
22.5 - A
Full temperature range
(3)
1.55 - - A
Logic inputs
V
il
IN, SD vs.
SGND
Low level logic threshold voltage - 0.95 - 1.45 V
V
ih
High level logic threshold voltage - 2 - 2.5 V
I
INh
IN vs.
SGND
IN logic “1” input bias current IN = 15 V 120 200 260 A
I
INl
IN logic “0” input bias current IN = 0 V - - 1 A
I
SDh
SD vs.
SGND
SD
logic “1” input bias current SD = 15 V - - 1 A
I
SDl
SD logic “0” input bias current SD = 0 V 14 17 23 A
Electrical characteristics L6494
8/18 DocID030317 Rev 2
R
PU_SD
SD vs.
SGND
SD
pull-up resistor - 185 250 310 k
R
PD_IN
IN vs.
SGND
IN pull-down resistor - 58 75 125 k
Dynamic characteristics (see Figure 3 and Figure 4)
t
on
SD vs.
LVG/HVG
High/low-side driver turn-on
propagation delay
V
OUT
= 0 V; V
BOOT
= V
CC
;
C
L
= 1 nF; V
i
= 0 to 3.3 V
- 85 120 ns
t
off
SD vs.
LVG/HVG;
IN vs.
LVG/HVG
High/low-side driver turn-off
propagation delay
- 85 120 ns
MT -
Delay matching, HS and LS turn-
on/off
(4)
---30ns
t
r
LVG, HVG
Rise time C
L
= 1 nF - 25 - ns
t
f
Fall time C
L
= 1 nF - 25 - ns
DT - Deadtime setting range
(5)
R
DT
= 0 , C
L
= 1 nF, 0.26 0.40 0.54 s
R
DT
= 100 k, C
L
= 1 nF,
C
DT
= 100 nF
2.10 2.70 3.30 s
R
DT
= 200 k, C
L
= 1 nF,
C
DT
= 100 nF
4.00 5.00 6.00 s
MDT - Matching deadtime
(5)
R
DT
= 0 , C
L
= 1 nF, - - 85 ns
R
DT
= 100 k, C
L
= 1 nF,
C
DT
= 100 nF
--350ns
R
DT
= 200 k, C
L
= 1 nF,
C
DT
= 100 nF
--700ns
1. V
BO
= V
BOOT
- V
OUT
.
2. R
DSON
is tested in the following way:
R
DSON
= [(V
CC
- V
BOOT1
) - (V
CC
- V
BOOT2
)] / [I
1
(V
CC
, V
BOOT1
) - I
2
(V
CC
, V
BOOT2
)]
where I
1
is the BOOT pin current when V
BOOT
= V
BOOT1
, I
2
when V
BOOT
= V
BOOT2
.
3. Characterized, not tested in production.
4. MT = max. (|
ton
(LVG) - t
off
(LVG)|, |t
on
(HVG) - t
off
(HVG)|, |t
off
(LVG) - t
on
(HVG)|, |t
off
(HVG) - t
on
(LVG)|).
5. MDT = | DT
LH
- DT
HL
| see Figure 4.
Table 5. Electrical characteristics (V
CC
= 15 V; T
J
= +25 °C; PGND = SGND) (continued)
Symbol Pin Parameter Test condition Min. Typ. Max. Unit
DocID030317 Rev 2 9/18
L6494 Electrical characteristics
18
Figure 3. SD timings
Figure 4. IN timings and deadtime




U
S
U
G
U
PO
U
PGG


4%
*/
 
)7(


U
S
U
G
U
PO
U
PGG


-7(
".




U
S
U
G
U
PGG


4%
*/
)7(

U
G
U
PGG

-7(
%5
-)
%5
)-

".

L6494LD

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Gate Drivers IND. & POWER CONV.
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet