ADUM4154ARIZ-RL Datasheet ADUM4154ARIZ, ADUM4154ARIZ-RL, ADUM4154BRIZ-RL | P19-P21

ADuM4154 Data Sheet

Rev. A | Page 18 of 22

Figure 11 shows how the ADuM4154 can control up to four

slaves by routing the

MSS

input to one of four outputs on the

slave side of the isolator, which eliminates three isolation

channels compared to the standard solution.

MASTER

ADuM4154

SLAVE 0CLK

MOSI

MISO

MUX

CLK

MOSI

MISO

SCLK

SS0

SLAVE 1

CLK

MOSI

MISO

SS1

SLAVE 2

CLK

MOSI

MISO

SS2

SLAVE 3

CLK

MOSI

MISO

SS3

ADDRESS0

ADDRESS1

SSA0

SSA1

MSS

MCLK

MSS

12366-011

Figure 11. Multiple Slave Control

The multiplexer select lines are low speed channels implemented as

part of the dc correctness scheme in the ADuM4154. The dc

value of all high and low speed inputs on a given side of the

device are sampled simultaneously, packetized, and shifted

across an isolation coil. The high speed channels are compared

for dc accuracy, and the low speed mux select lines, SSA0 and

SSA1, are transferred to the mux control block. The dc

correctness data for the high speed channels is handled

internally with no visibility off chip.

This data is regulated by a free running internal clock. Because data

is sampled at discrete times based on this clock, the propagation

delay for mux select lines is between 0.1 μs and 2.6 μs, depending

on where the input data edge changes with respect to the internal

sample clock. After an address propagation delay time of up to

2.6 μs, the multiplexer routes the

MSS

signals to the desired output.

The outputs that are not selected are set to high-Z, and the

application pulls them to the desired idle state.

Figure 12 illustrates the behavior of the SSA0 and SSA1

channels. This diagram assumes that

MSS

is low and that SS0,

SS1, SS2, and SS3 are pulled up.

SSA0

SS0

SAMPLE CLOCK

OUTPUT CLOCK

SSA1

SS1

SS2

SS3

12366-012

Figure 12. Mux Select Timing

The following details the mux select timing shown in Figure 12:

 Point A: The mux select lines must be switched

simultaneously to within the t

SSAx SKEW

time. Failure to do

this may allow sampling the inputs between the edges and

selecting an incorrect mux output. Point A on SS1 is a

metastable state on the output mux resulting from wide

spacing between SSA0 and SSA1.

 Point B: For mux select lines to be processed predictably, a

state of SSA0 and SSA1 must be stable for longer than 4 μs

before switching the mux to another output. This

guarantees that at least two samples are taken of the inputs

before the mux output is changed.

 Point C: This point in Figure 12 shows a clean transfer

between SS3 being active and SS0 being active. The mux

was designed to eliminate any short duration metastable

states between any two selected outputs.

Data Sheet ADuM4154

Rev. A | Page 19 of 22

PRINTED CIRCUIT BOARD (PCB) LAYOUT

The ADuM4154 digital isolator requires no external interface

circuitry for the logic interfaces. Power supply bypassing is

strongly recommended at both the V

DD1

and V

DD2

supply pins

(see Figure 13). The capacitor value must be between 0.01 μF

and 0.1 μF. The total lead length between both ends of the

capacitor and the input power supply pin must not exceed

20 mm.

BYPASS < 10mm

DD1

GND

MCLK

MSS

SSA0

SSA1

DD2

GND

SCLK

SS0

SS1

SS2

NIC

GND

SS3

GND

ADuM4154

TOP VIEW

(Not to Scale)

12366-013

Figure 13. Recommended PCB Layout

In applications involving high common-mode transients, it is

important to minimize board coupling across the isolation barrier.

Furthermore, design the PCB layout so that any coupling that

does occur affects all pins equally on a given component side.

Failure to ensure this may cause voltage differentials between

pins that exceed the absolute maximum ratings of the device,

thereby leading to latch-up or permanent damage.

PROPAGATION DELAY RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes

a logic signal to propagate through a component. The input to

output propagation delay time for a high to low transition may

differ from the propagation delay time of a low to high

transition.

INPUT

OUTPUT

PLH

PHL

50%

12366-014

Figure 14. Propagation Delay Parameters

Pulse width distortion is the maximum difference between

these two propagation delay values and an indication of how

accurately the timing of the input signal is preserved.

Channel to channel matching refers to the maximum amount

the propagation delay differs between channels within a single

ADuM4154 component.

DC CORRECTNESS AND MAGNETIC FIELD

IMMUNITY

Positive and negative logic transitions at the isolator input cause

narrow (~1 ns) pulses to be sent via the transformer to the

decoder. The decoder is bistable and is, therefore, either set or

reset by the pulses indicating input logic transitions. In the

absence of logic transitions at the input for more than ~1.2 μs, a

periodic set of refresh pulses indicative of the correct input state

are sent via the low speed channel to ensure dc correctness at

the output.

If the low speed decoder receives no pulses for more than about

5 μs, the input side is assumed to be unpowered or nonfunctional,

in which case, the isolator output is forced to a high-Z state by

the watchdog timer circuit.

The limitation on the magnetic field immunity of the device is

set by the condition in which induced voltage in the transformer

receiving coil is sufficiently large to either falsely set or reset the

decoder. The following analysis defines such conditions. The

ADuM4154 is examined in a 3 V operating condition because it

represents the most susceptible mode of operation for this

product.

The pulses at the transformer output have an amplitude greater

than 1.5 V. The decoder has a sensing threshold of about 1.0 V;

thereby establishing a 0.5 V margin in which induced voltages

can be tolerated. The voltage induced across the receiving coil is

given by

V = (−dβ/dt)Σπr

; n = 1, 2, …, N

where:

β is the magnetic flux density.

is the radius of the n

turn in the receiving coil.

N is the number of turns in the receiving coil.

Given the geometry of the receiving coil in the ADuM4154 and

an imposed requirement that the induced voltage be, at most,

50% of the 0.5 V margin at the decoder, a maximum allowable

magnetic field is calculated, as shown in Figure 15.

MAGNETIC FIELD FREQUENCY (Hz)

MAXIMUM ALLOWABLE MAGNETIC FLUX

DENSITY (kgauss)

0.001

100

100M

0.1

0.01

10k 100k 1M 10M

12366-015

Figure 15. Maximum Allowable External Magnetic Flux Density

ADuM4154 Data Sheet

For example, at a magnetic field frequency of 1 MHz, the

maximum allowable magnetic field of 0.5 kgauss induces a

voltage of 0.25 V at the receiving coil. This voltage is about 50%

of the sensing threshold and does not cause a faulty output

transition. If such an event occurs, with the worst-case polarity,

during a transmitted pulse, the interference reduces the received

pulse from >1.0 V to 0.75 V. This voltage is still well above the

0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to

specific current magnitudes at given distances away from the

ADuM4154 transformers. Figure 16 expresses these allowable

current magnitudes as a function of frequency for selected

distances. The ADuM4154 is insensitive to external fields. Only

extremely large, high frequency currents very close to the

component are potentially a concern. For the 1 MHz example

noted, placing a 1.2 kA current 5 mm away from the

ADuM4154 affects component operation.

MAGNETIC FIELD FREQUENCY (Hz)

MAXIMUM ALLOWABLE CURRENT (kA)

1000

100

0.1

0.01

1k 10k

100M100k 1M 10M

DISTANCE = 5mm

DISTANCE = 1m

DISTANCE = 100mm

12366-016

Figure 16. Maximum Allowable Current for

Various Current to ADuM4154 Spacings

At combinations of a strong magnetic field and high frequency,

any loops formed by the PCB traces may induce sufficiently

large error voltages to trigger the thresholds of succeeding

circuitry. Take care to avoid PCB structures that form loops.

POWER CONSUMPTION

The supply current at a given channel of the ADuM4154

isolator is a function of the supply voltage, the data rate of the

channel, the output load of the channel, and whether it is a high

or low speed channel.

The low speed channels draw a constant quiescent current

caused by the internal ping-pong datapath. The operating

frequency is low enough that the capacitive losses caused by

the recommended capacitive load are negligible compared to

the quiescent current. The explicit calculation for the data rate

is eliminated for simplicity, and the quiescent current for each

side of the isolator due to the low speed channels can be found

in Table 3, Table 5, Table 7, and Table 9 for the particular operating

voltages.

These quiescent currents add to the high speed current as is

shown in the following equations for the total current for each

side of the isolator. Dynamic currents are taken from Table 3

and Table 5 for the respective voltages.

For Side 1, the supply current is given by

DD1

= I

DDI(D)

× (f

MCLK

+ f

MSS

) + f

DDO(D)

+ ((0.5 × 10

−3

) × C

L(MI)

× V

DD1

)) + I

DD1(Q)

For Side 2, the supply current is given by

DD2

= I

DDI(D)

× f

SCLK

× (I

DDO(D)

+((0.5 × 10

−3

) × C

L(SCLK)

× V

DD2

)) +

× (I

DDO(D)

+((0.5 × 10

−3

) × C

L(SI)

× V

DD2

)) +

SSx

× (I

DDO(D)

+((0.5 × 10

−3

) × C

L(SSx)

× V

DD2

)) + I

DD2(Q)

where:

DDI(D)

, I

DDO(D)

are the input and output dynamic supply currents

per channel (mA/Mbps).

is the logic signal data rate for the specified channel (Mbps).

DD1(Q)

, I

DD2(Q)

are the specified Side 1 and Side 2 quiescent

supply currents (mA).

L(x)

is the load capacitance of the specified output (pF).

DDx

is the supply voltage of the side being evaluated (V).

Figure 4 and Figure 7 show the typical supply current per

channel as a function of data rate for an input and unloaded

output. Figure 5 and Figure 8 show the total I

DD1

and I

DD2

supply

currents as a function of data rate for ADuM4154 channel

configurations with all high speed channels running at the same

speed and the low speed channels at idle.

INSULATION LIFETIME

All insulation structures eventually break down when subjected

to voltage stress over a sufficiently long period. The rate of

insulation degradation is dependent on the characteristics of the

voltage waveform applied across the insulation, as well as the

materials and material interfaces.

Two types of insulation degradation are of primary interest:

breakdown along surfaces exposed to the air and insulation

wear out. Surface breakdown is the phenomenon of surface

tracking and the primary determinant of surface creepage

requirements in system level standards. Insulation wear out is

the phenomenon where charge injection or displacement

currents inside the insulation material cause long-term

insulation degradation.

Rev. A | Page 20 of 22

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

ADUM4154ARIZ-RL

Mfr. #:

Buy ADUM4154ARIZ-RL

Manufacturer:

Analog Devices Inc.

Description:

Digital Isolators Multip Slave Isolatr for SPI Intrface

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

ADUM4154ARIZ-RL

ADUM4154ARIZ-RL

Products related to this Datasheet