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ADUM4154ARIZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
ADuM4154 Data Sheet
Table 5. For All Models
1, 2, 3
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT
A Grade and B Grade I
DD1
3.4 6.5 mA C
L
= 0 pF, DR
FAS T
= 1 MHz,
DR
SLOW
= 0 MHz
I
DD2
5 9 mA C
L
= 0 pF, DR
FAS T
= 1 MHz,
DR
SLOW
= 0 MHz
B Grade I
DD1
11.7 15 mA C
L
= 0 pF, DR
FAS T
= 17 MHz,
DR
SLOW
= 0 MHz
I
DD2
10 14 mA C
L
= 0 pF, DR
FAS T
= 17 MHz,
DR
SLOW
= 0 MHz
DC SPECIFICATIONS
MCLK,
MSS
, MO, SO, SSA0, SSA1
Input Threshold
Logic High V
IH
0.7 × V
DDx
V
Logic Low V
IL
0.3 × V
DDx
V
Input Hysteresis V
IHYST
500 mV
Input Current per Channel I
I
−1 +0.01 +1 µA 0 V ≤ V
INPUT
≤ V
DDx
SCLK, MI, SI, SS0, SS1, SS2, SS3
Output Voltages
Logic High V
OH
V
DDx
− 0.1 5.0 V I
OUTPUT
= −20 µA, V
INPUT
= V
IH
V
DDx
− 0.4 4.8 V I
OUTPUT
= −4 mA, V
INPUT
= V
IH
Logic Low V
OL
0.0 0.1 V I
OUTPUT
= 20 µA, V
INPUT
= V
IL
0.2 0.4 V I
OUTPUT
= 4 mA, V
INPUT
= V
IL
V
DD1
, V
DD2
Undervoltage Lockout
UVLO
2.6
V
Supply Current per High Speed Channel
Dynamic Input I
DDI(D)
0.078 mA/Mbps
Dynamic Output I
DDO(D)
0.026 mA/Mbps
Supply Current for All Low Speed Channels
Quiescent Input I
DD1(Q)
2.9 mA
Quiescent Output I
DD2(Q)
4.7 mA
AC SPECIFICATIONS
Output Rise/Fall Time t
R
/t
F
2.5 ns 10% to 90%
Common-Mode Transient Immunity
4
|CM| 25 35 kV/µs V
INPUT
= V
DDx
, V
CM
= 1000 V,
transient magnitude = 800 V
1
V
DDx
= V
DD1
or V
DD2
.
2
V
INPUT
is the input voltage of any of the MCLK,
MSS
, MO, SO, SSA0, or SSA1 pins.
3
I
OUTPUT
is the output current of any of the SCLK, MI, SI, SS0 SS1, SS2, or SS3 pins.
4
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the V
OH
and V
OL
limits. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. A | Page 6 of 22
Data Sheet ADuM4154
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OPERATION
All typical specifications are at T
A
= 25°C and V
DD1
= 5 V, V
DD2
= 3.3 V. Minimum and maximum specifications apply over the entire
recommended operation range: 4.5 V ≤ V
DD1
≤ 5.5 V, 3.0 V ≤ V
DD2
≤ 3.6 V, and −40°C ≤ T
A
≤ +125°C, unless otherwise noted. Switching
specifications are tested with C
L
= 15 pF and CMOS signal levels, unless otherwise noted.
Table 6. Switching Specifications
Parameter Symbol
A Grade B Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
MCLK, MO, SO
SPI Clock Rate SPI
MCLK
1 15.6 MHz
Data Rate Fast (MO, SO) DR
FAS T
2 34 Mbps Within PWD limit
Propagation Delay t
PHL
, t
PLH
27 17 ns 50% input to 50% output
Pulse Width PW 25 12.5 ns Within PWD limit
Pulse Width Distortion PWD 2 2 ns |t
PLH
− t
PHL
|
Codirectional Channel Matching
1
t
PSKCD
2 2 ns
Jitter, High Speed
J
HS
1
1
ns
MSS
Data Rate Fast DR
FAS T
2 34 Mbps Within PWD limit
Propagation Delay t
PHL
, t
PLH
30 30 ns 50% input to 50% output
Pulse Width PW 25 12.5 ns Within PWD limit
Pulse Width Distortion PWD 2 2 ns |t
PLH
− t
PHL
|
Setup Time
2
MSS
SETUP
1.5 10 ns
Jitter, High Speed J
HS
1 1 ns
SSA0, SSA1
Data Rate Slow DR
SLOW
250 250 kbps Within PWD limit
Propagation Delay t
PHL
, t
PLH
0.1 2.6 0.1 2.6 µs 50% input to 50% output
Pulse Width PW 4 4 µs Within PWD limit
Jitter, Low Speed J
LS
2.5 2.5 µs |t
PLH
− t
PHL
|
SSAx
3
Minimum Input Skew
4
t
SSAx SKEW
3
40 40 ns
1
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier.
2
The
MSS
signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that
MSS
reaches the output
ahead of another fast signal, set up
MSS
prior to the competing signal by different times depending on speed grade.
3
SSAx = SSA0 or SSA1.
4
An internal asynchronous clock, not available to users, samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the
leading pulse must be at least 1 t
SSAx SKEW
ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
Rev. A | Page 7 of 22
ADuM4154 Data Sheet
Table 7. For All Models
1, 2, 3
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT
A Grade and B Grade I
DD1
4.8 8.5 mA C
L
= 0 pF, DR
FAS T
= 1 MHz,
DR
SLOW
= 0 MHz
I
DD2
5 9 mA C
L
= 0 pF, DR
FAS T
= 1 MHz,
DR
SLOW
= 0 MHz
B Grade I
DD1
10 18 mA C
L
= 0 pF, DR
FAS T
= 17 MHz,
DR
SLOW
= 0 MHz
I
DD2
10 14 mA C
L
= 0 pF, DR
FAS T
= 17 MHz,
DR
SLOW
= 0 MHz
DC SPECIFICATIONS
MCLK,
MSS
, MO, SO, SSA0, SSA1
Input Threshold
Logic High V
IH
0.7 × V
DDx
V
Logic Low V
IL
0.3 × V
DDx
V
Input Hysteresis V
IHYST
500 mV
Input Current per Channel I
I
−1 +0.01 +1 µA 0 V ≤ V
INPUT
≤ V
DDX
SCLK, MI, SI, SS0, SS1, SS2, SS3
Output Voltages
Logic High V
OH
V
DDx
− 0.1 5.0 V I
OUTPUT
= −20 µA, V
INPUT
= V
IH
V
DDx
− 0.4 4.8 V I
OUTPUT
= −4 mA, V
INPUT
= V
IH
Logic Low V
OL
0.0 0.1 V I
OUTPUT
= 20 µA, V
INPUT
= V
IL
0.2 0.4 V I
OUTPUT
= 4 mA, V
INPUT
= V
IL
V
DD1
, V
DD2
Undervoltage Lockout
UVLO
2.6
V
Supply Current for All Low Speed Channels
Quiescent Input I
DD1(Q)
4.2 mA
Quiescent Output I
DD2(Q)
4.7 mA
AC SPECIFICATIONS
Output Rise/Fall Time t
R
/t
F
2.5 ns 10% to 90%
Common-Mode Transient Immunity
4
|CM| 25 35 kV/µs V
INPUT
= V
DDx
, V
CM
= 1000 V,
transient magnitude = 800 V
1
V
DDx
= V
DD1
or V
DD2
.
2
V
INPUT
is the input voltage of any of the MCLK,
MSS
, MO, SO, SSA0, or SSA1 pins.
3
I
OUTPUT
is the output current of any of the SCLK, MI, SI, SS0, SS1, SS2, or SS3 pins.
4
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the V
OH
and V
OL
limits. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. A | Page 8 of 22
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

ADUM4154ARIZ-RL

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Manufacturer:
Analog Devices Inc.
Description:
Digital Isolators Multip Slave Isolatr for SPI Intrface
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