NCP1234
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16
Figure 29. Fast Application Off − On Sequence
time
V
HV
time
V
CC
time
Output
V
HV(min)
V
CC(on)
V
CC(min)
The board is
unplugged
Controller
stops at
V
CC(off)
V
CC(off)
time
DRV
time
Fault timer
(internal)
VCC charges
up when V
HV
is
high enough
Loss of
regulation when
V
HV
is too low
Switching
restarts at
V
CC(on)
Fault timer
reset by
V
CC(off)
NCP1234
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17
Oscillator with Maximum Duty Cycle and Frequency
Jittering
The NCP1234 includes an oscillator that sets the
switching frequency with an accuracy of ±7%. Two
frequency options can be ordered: 65 kHz and 100 kHz. The
maximum duty cycle of the DRV pin is 80%, with an
accuracy of ±7%.
In order to improve the EMI signature, the switching
frequency jitters ±6% around its nominal value, with a
triangle−wave shape and at a frequency of 125 Hz. This
frequency jittering is active even when the frequency is
decreased to improve the EMI in light load condition.
Time
8%
(125 Hz)
Figure 30. Frequency Jittering
f
OSC
f
OSC
+ 6
Nominal f
OSC
f
OSC
− 6
Clamped Driver
The supply voltage for the NCP1234 can be as high as
28 V, but most of the MOSFETs that will be connected to the
DRV pin cannot accept more than 20 V on their gate. The
driver pin is therefore clamped safely below 16 V. This
driver has a typical current capability of ±500 mA.
Figure 31. Clamped Driver
DRV
Clamp
DRV signal
VCC
NCP1234
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18
CURRENT−MODE CONTROL WITH OVERPOWER COMPENSATION AND SOFT−START
Current sensing
NCP1234 is a current−mode controller, which means that
the FB voltage sets the peak current flowing in the
inductance and the MOSFET. This is done through a PWM
comparator: the current is sensed across a resistor and the
resulting voltage is applied to the CS pin. It is applied to one
input of the PWM comparator through a 250 ns LEB block.
On the other input the FB voltage divided by 5 sets the
threshold: when the voltage ramp reaches this threshold, the
output driver is turned off.
The maximum value for the current sense is 0.7 V, and it
is set by a dedicated comparator.
Figure 32. Current Sense Block Schematic
CS
FB
+
t
LEB
blanking
K
FB
R
FB(up)
+
+
+
+
+
V
ILIM
V
CS(stop)
S
R
Q
t
SSTART
Soft−start ramp
Start
Reset
IC Start
IC Stop
Oscillator
Protection
Mode
UVLO
Jitter
Latch
Soft−start
IC stop
TSD
Fault
DRV Stage
blanking
PWM
t
BCS
V
FB(ref)
Each time the controller is starting, i.e. the controller was
off and starts – or restarts – when V
CC
reaches V
CC(on)
, a
soft−start is applied: the current sense setpoint is linearly
increased from 0 (the minimum level can be higher than 0
because of the LEB and propagation delay) until it reaches
V
ILIM
(after a duration of t
SSTART
), or until the FB loop
imposes a setpoint lower than the one imposed by the
soft−start (the 2 comparators outputs are OR’ed). The
soft−start ramp signal is generated by the D/A converter in
the NCP1234, that’s why there are observable 15 discrete
steps instead the truly linearly increasing current setpoint
ramp.

NCP1234BD100R2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers Fixed Freq (I) Mode For FlyBk Conv
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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