NCP1234
www.onsemi.com
27
Time
Time
DRV
Enters
skip
Exits
skip
Enters
skip
Exits
skip
Figure 45. Skip Cycle Timing Diagram
V
FB
V
FB(fold)
V
skip(out)
V
skip(in)
Latch−off Input
Figure 46. Latch Detection Schematic
−
+
Latch
VOVP
S
R
Q
−
+
VOTP
tLatch(OVP)
blanking
VDD
Reset
Latch
Vclamp
INTC
tLatch(OTP)
blanking
1 kW
I
NTC
+
+
Soft−start
end
The Latch pin is dedicated to the latch−off function: it
includes two levels of detection that define a working
window, between a high latch and a low latch: within these
two thresholds, the controller is allowed to run; but as soon
as either the low or the high threshold is crossed, the
controller is latched off. The lower threshold is intended to
be used with an NTC thermistor, thanks to an internal current
source I
NTC
.
An active clamp prevents the voltage from reaching the
high threshold if it is only pulled up by the I
NTC
current. To
reach the high threshold, the pull−up current has to be higher
than the pull−down capability of the clamp (typically
1.5 mA at V
OVP
).
To avoid any false triggering, spikes shorter than 50 ms
(for the high latch and 65 kHz version) or 350 ms (for the low
latch) are blanked and only longer signals can actually latch
the controller.
Reset occurs when V
CC
is cycled down to a reset voltage,
which in a real application can only happen if the power
supply is unplugged from the AC line.
Upon start−up, the internal references take some time
before being at their nominal values; so one of the
comparators could toggle even if it should not. Therefore the
internal logic does not take the latch signal into account
before the controller is ready to start: once V
CC
reaches
V
CC(on)
, the latch pin High latch state is taken into account
