Functional Block Diagram
Figure 2: Functional Block Diagram
Group A
(Address/Command/Control/ Clock)
36 TwinDie DRAM in 4 Module Rank Configuration
Group B
(Address/Command/Control/Clock)
CKE2A/B,
ODT0A/B,
CS2
CKE3A/B,
ODT1A/B,
CS3
CKE1A/B, ODT1A/B, CS1
CKE0A/B, ODT0A/B, CS0
Rank 1
Memory Buffer
SPD/EEPROM
Temp Sensor
EVENT#
Temp
Sensor
Configuration
and
Status Registers
EVENT#
SMBus
DQS[17:0]
DQS#[17:0]
DQ[63:0]
CB[7:0]
Data and Strobes
CK0
CK0#
S#[3:0]
BA[2:0]
A[15:0]
1
Par_In
RAS#
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
RESET#
Address/Command/Control/Clock
Err_Out#
V
REFCA
V
REFDQ
Rank
Multiplication
A15
1
S#[1:0]
S2#/A16
S3#/A17
Rank
Multiplier
Data and Strobes
Rank 2
Rank 0
Rank 3
Notes:
1. The ZQ ball on each DDR3 die is connected to a separate external 240Ω ±1% resistor
that is tied to V
SS
. This supports ZQ calibration to the entire device with one command
set. It is used for the calibration of the component’s ODT and output driver.
2. A15 used for rank multiplication for 16GB module and for DRAM addressing for 32GB
module.
32GB (x72, ECC, QR) 240-Pin DDR3 LRDIMM
Functional Block Diagram
PDF: 09005aef83b62686
jszs72c4gx72lz.pdf - Rev. F 2/15 EN
9
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