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A. All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, frequency = 50 MHz, duty cycle = 50
±5%. C
L is a combination of a 20%−tolerance, low−loss ceramic, surface−mount capacitor and fixture capacitance within 2 cm of the
D.U.T.
B. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 12. Receiver Timing Test Circuit and Waveforms
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A. All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, frequency = 500 kHz, duty cycle = 50
±5%.
B. RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T.
C. C
L is the instrumentation and fixture capacitance within 2 cm of the DUT and 20%.
Figure 13. Receiver Enable/Disable Time Test Circuit and Waveforms
NBA3N206S
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12
A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 100 MHz 50 ±1% duty cycle clock input.
D. Peak−to−peak jitter is measured using a 200 Mbps 2
15
−1 PRBS input.
Figure 14. Receiver Jitter Measurement Waveforms
Table 8. TYPE−2 RECEIVER INPUT THRESHOLD TEST VOLTAGES
Applied Voltages
Resulting Differential
Input Voltage
Resulting Common−
Mode Input Voltage
Receiver Output
(Note )
VIA VIB VID VIC
2.400 0.000 2.400 1.200 H
0.000 2.400 –2.400 1.200 L
3.800 3.650 0.150 3.725 H
3.800 3.750 0.050 3.775 L
–1.250 –1.400 0.150 –1.325 H
–1.350 –1.400 0.050 –1.375 L
H = high level, L = low level, output state assumes receiver is enabled (RE = L)

NBA3N206SDG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer MLVDS DRIVER RECEIVER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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