NBA3N206S
www.onsemi.com
14
APPLICATION INFORMATION
Receiver Input Threshold (Failsafe)
The MLVDS standard defines a type 1 and type 2 receiver.
Type 1 receivers include no provisions for failsafe and have
their differential input voltage thresholds near zero volts.
Type 2 receivers have their differential input voltage
thresholds offset from zero volts to detect the absence of a
voltage difference. The impact to receiver output by the
offset input can be seen in Table 9 and Figure 16.
Table 9. RECEIVER INPUT VOLTAGE THRESHOLD REQUIREMENTS
Receiver Type Output Low Output High
Type 1 –2.4 V ≤ VID ≤ –0.05 V 0.05 V ≤ VID ≤ 2.4 V
Type 2 –2.4 V ≤ VID ≤ 0.05 V 0.15 V ≤ VID ≤ 2.4 V
Figure 16. Receiver Differential Input Voltage Showing Transition Regions by Type
NBA3N206S
LIVE INSERTION/GLITCH−FREE POWER UP/DOWN
The NBA3N206S provides a glitch−free power up/down
feature that prevents the M−LVDS outputs of the device
from turning on during a power up or power down event.
This is especially important in live insertion applications,
when a device is physically connected to an M−LVDS
multipoint bus and V
CC
is ramping.
While the M−LVDS interface for these devices is glitch
free on power up/down, the receiver output structure is not.
Figure 17 shows the performance of the receiver output pin,
R (CHANNEL 2), as V
CC
(CHANNEL 1) is ramped. The
glitch on the R pin is independent of the RE voltage. Any
complications or issues from this glitch are easily resolved
in power sequencing or system requirements that suspend
operation until V
CC
has reached a steady state value.
