NCP1339
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22
Fault
NTC
Vaux
Latch
Vfault(OVP)
Vfault(OTP)
S
R
Q
Q
BONOK
Ifault(OTP)
Rfault(clamp)
Vfault(clamp)
5 V
Figure 50. Fault Detection Schematic
As a matter of fact, the controller operates normally while
the Fault pin voltage is maintained within the upper and
lower fault thresholds. Upper and lower fault detector have
blanking delays to prevent noise from triggering them. Both
blanking timers (t
delay(Fault_OVP)
and t
delay(Fault_OTP)
) are
typically 27.5 ms.
When the part is latched−off, the drive is immediately
turned off. Also, V
CC
drops and stabilize to the 5.5−V
V
CC(bias)
level. The power supply needs to be un−plugged to
reset the part as a result of a BONOK (BO fault condition)
and/or the X2 circuitry activation.
PSM mode cannot be triggered in latched−off mode.
Zero Current Detection
The NCP1339 integrates a quasi−resonant (QR) flyback
controller. The power switch turn−off of a QR converter is
determined by the peak current set by the feedback loop. The
switch turn−on is determined by the transformer
demagnetization. The demagnetization is detected by
monitoring the transformer auxiliary winding voltage.
Turning on the power switch once the transformer is
demagnetized or reset reduces switching losses. Once the
transformer is demagnetized, the drain voltage starts ringing
at a frequency determined by the transformer magnetizing
inductance and the drain lump capacitance eventually
settling at the input voltage. A QR controller takes
advantage of the drain voltage ringing and turns on the
power switch at the drain voltage minimum or “valley” to
reduce switching losses and electromagnetic interference
(EMI).
As sketched by Figure 51, a valley is detected once the
ZCD pin voltage falls below the QR flyback
demagnetization threshold, V
ZCD(th)
, typically 55 mV. The
controller will switch once the valley is detected or
increment the valley counter depending on FB voltage.
Timeout
The ZCD block actually detects falling edges of the
auxiliary winding voltage applied to the ZCD pin. At
start−up or other transient phases, the ZCD comparator may
be unable to detect such an event. Also, in the case of
extremely damped oscillations, the system may not succeed
in detecting all the valleys required by VLO operation (see
next section). In this condition, the NCP1339 ensures
continued operation by incorporating a maximum timeout
period that resets when a demagnetization phase is detected.
The timeout signal substitutes ZCD signal for the valley
counter. Figure 51 shows the timeout period generator
circuit schematic. The steady state timeout period, t
(out2)
, is
set at 6 ms.
During startup, the output voltage is still low leading to
long demagnetization phases difficult to detect since the
auxiliary winding voltage is small as well. In this condition,
the 6−ms steady−state timeout is generally shorter than the
inductor demagnetization period and if used to restart a
switching cycle, it can cause continuous current mode
(CCM) operation for few cycles until the voltage on the ZCD
pin is high enough for proper valleys detection. A longer
timeout period, t
(out1)
, (typically 100 ms) is therefore set
during soft−start to prevent CCM operation.
In VLO operation, the timeout periods of time are counted
instead of valleys when the drain−source voltage
oscillations are too damped to be detected. For instance, if
the circuit must turn on at the fifth valley and if the ZCD
ringing only enables to detect:
Valleys 1 to 4: the circuit generates a DRV pulse 6 ms
(steady−state timeout delay) after valley 4 detection.
Valleys 1 to 3: the timeout delay must run twice so that
the circuit generates a DRV pulse 12 ms after valley 3
detection.
NCP1339
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23
ZCD
+
Vzcd(th)
Rzcd
Czcd
DRV
(internal)
Blanking Time
Tzcd(blank)
Timeout
QR
Logic
Figure 51. Valley Lockout Detection Circuitry Internal Schematic
Valley Lockout (VLO) and Frequency Foldback (FF)
The operating frequency of a traditional QR flyback
controller is inversely proportional to the system load. In
other words, a load reduction increases the operating
frequency. A maximum frequency clamp can be useful to
limit the operating frequency range. However such an
approach causes instabilities since when this clamp is active,
the controller tends to jump (or hesitate) between two
valleys generating audible noise.
Instead, the NCP1339 incorporates a patent pending
valley lockout circuitry to eliminate valley jumping. Once a
valley is selected, the controller stays locked in this valley
until the output power changes significantly. This technique
extends QR operation over a wider output power range
while maintaining good efficiency and limiting the
maximum operating frequency.
The operating valley (1
st
, 2
nd
, 3
rd,
4
th
, 5
th
or 6
th
) is
determined by the FB voltage. As V
FB
decreases or
increases, the valley comparators toggle one after another to
select the proper valley. The decimal counter increases each
time a valley is detected. The activation of an “n” valley
comparator blanks the “n−1” or “n+1” valley comparator
output depending if V
FB
decreases or increases,
respectively. Figure 52 shows a typical frequency
characteristic obtainable at low line in a 60−W application.
0 20 40 60
0
210
4
x
410
4
x
610
4
x
810
4
x
110
5
x
Pout (W)
Fsw(Hz)
1
st
2
nd
3
rd
4
th
5
th
6
th
VCO
mode
1
st
2
nd
3
rd
4
th
5
th
6
th
VCO
mode
Figure 52. Valley Lockout Frequency vs Output Power Relationship
NCP1339
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24
When an “n” valley is asserted by the valley selection
circuitry, the controller is locked in this valley until the FB
voltage decreases to the lower threshold (“n+1” valley
activates) or increases to the “n valley threshold” + 600 mV
(“n−1” valley activates). The regulation loop adjusts the
peak current to deliver the necessary output power. Each
valley selection comparator features a 600−mV hysteresis
that helps stabilize operation despite the FB voltage swing
produced by regulation loop.
Valley FB Thresholds (typical values):
FB Falling FB Rising
1
st
to 2
nd
valley 1.4 V FF mode to 6
th
valley 1.0 V
2
nd
to 3
rd
valley 1.2 V 6
th
to 5
th
valley 1.5 V
3
rd
to 4
th
valley 1.1 V 5
th
to 4
th
valley 1.6 V
4
th
to 5
th
valley 1.0 V 4
th
to 3
rd
valley 1.7 V
5
th
to 6
th
valley 0.9 V 3
rd
to 2
nd
valley 1.8 V
6
th
valley to FF mode 0.8 V 2
nd
to 1
st
valley 2.0 V
Frequency Foldback
As the output load decreases (FB voltage decreases), the
valleys are incremented from 1 to 6. For versions without
IFF pin, if when the sixth valley is reached, the FB voltage
further decreases below 0.8 V, the controller enters the
frequency foldback mode (FF). The current setpoint being
internally forced to remain above 0.2 V (setpoint
corresponding to V
FB
= 0.8 V), the controller regulates the
power delivery by modulating the switching frequency.
When a load increase causes FB to exceed the 1−V FF upper
threshold (200−mV hysteresis), the circuit recovers VLO
operation.
For versions with the IFF pin available, both frequency
foldback threshold and frozen peak current are adjustable.
Thanks to an external pull down resistor combined with the
internal pull up current source (
I
FF(bias)
), the voltage develops
across this resistor will determine when the controller enters
in FF mode. In FF operation, the peak current is frozen to
(V
IFF
/4). When as a result of a load increase, FB exceeds
back the (V
IFF
+ 200 mV) level (200 mV hysteresis), the
circuit recovers VLO operation.
In frequency foldback mode, the system reduces the
switching frequency by adding some dead−time after the 6
th
valley is detected. This dead−time increases when the FB
voltage decays. There is no discontinuity when the system
transitions from VLO to FF and the frequency smoothly
reduces as FB goes below 0.8 V (or V
IFF
).
The dead−time is dimensioned to generate a 2−ms
dead−time when V
FB
= 0.8 V and could linearly go to
virtually infinity as V
FB
falls down to 0.4 V if the switching
was not forced to keep above 25−kHz to eliminate risk of
audible noise.
Figure 53 summarizes the operation mode with respect to
the FB voltage for versions without IFF pin (fixed internally
to 0.8 V).
25−kHz Frequency Clamp and Skip Mode
As aforementioned, the circuit prevents the switching
frequency from dropping below 25 kHz. When the
switching cycle is longer than 40 ms, the circuit forces a new
switching cycle. However, the 25−kHz frequency clamp
cannot generate a DRV pulse until the demagnetization is
completed. In other words, it cannot cause operation in
continuous conduction mode.
Since the NCP1339 forces a minimum peak current (as
aforementioned, the circuit prevents the peak current from
dropping below (0.2 V / R
SENSE
or (V
IFF
/4) / R
SENSE
)
where R
SENSE
is the current sense resistor) and a minimum
frequency (25 kHz typically), the power delivery cannot be
continuously controlled down to zero. Instead, the circuit
stops pulsing when the FB voltage drops below 400 mV and
recovers operation when V
FB
exceeds 450 mV (50−mV
hysteresis). This skip−mode method provides an efficient
power control in light load.

NCP1339HDR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers HIGH VOLTAGE QUASI R
Lifecycle:
New from this manufacturer.
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