8
ST16C552/552A
Rev. 3.40
Symbol Pin Signal Type Pin Description
UART RX Inputs, internally.
TX A/B 26,10 O Transmit Data, TX A-B - These outputs are associated with
individual serial transmit channel(s) from the 552/552A.
The TX signal will be a logic 1 during reset, idle (no data),
or when the transmitter is disabled. During the local loop-
back mode, the TX output pins are disabled and TX data is
internally connected to the UART RX Inputs.
GENERAL DESCRIPTION
The 552/552A provides serial asynchronous receive
data synchronization, parallel-to-serial and serial-to-
parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for
converting the serial data stream into parallel data that
is required with digital data systems. Synchronization
for the serial data stream is accomplished by adding
start and stops bits to the transmit data to form a data
character (character orientated protocol). Data integ-
rity is insured by attaching a parity bit to the data
character. The parity bit is checked by the receiver for
any transmission bit errors. The electronic circuitry to
provide all these functions is fairly complex especially
when manufactured on a single integrated silicon
chip. The 552/552A represents such an integration
with greatly enhanced features. The 552/552A is
fabricated with an advanced CMOS process.
The 552/552A is an upward solution that provides 16
bytes of transmit and receive FIFO memory, instead
of none in the 16C452. The 552/552A is designed to
work with high speed modems and shared network
environments, that require fast data processing time.
Increased performance is realized in the 552/552A by
the transmit and receive FIFO’s. This allows the
external processor to handle more networking tasks
within a given time. For example, the ST16C452
without a receive FIFO, will require unloading of the
RHR in 95.5 microseconds (This example uses a
character length of 11 bits, including start/stop bits at
115.2Kbps). This means the external CPU will have to
service the receive FIFO every 100 microseconds.
However with the 16 byte FIFO in the 552/552A, the data
buffer will not require unloading/loading for 1.53 ms. This
increases the service interval giving the external CPU
additional time for other applications and reducing the
overall UART interrupt servicing time. In addition, the 4
selectable levels of FIFO trigger interrupt is uniquely
provided for maximum data throughput performance
especially when operating in a multi-channel environ-
ment. The FIFO memory greatly reduces the bandwidth
requirement of the external controlling CPU, increases
performance, and reduces power consumption.
The 552/552A combines the package functions of a
dual UART and a printer interface on a single inte-
grated chip. The 552/552A UART is indented to be
software compatible with the INS8250/NS16C550
while the bi-directional printer interface mode is in-
tended to operate with a CENTRONICS type parallel
printer. However, the printer interface is designed
such that it may be configured to operate with other
parallel printer interfaces or used as a general purpose
parallel interface. The 552/552A is available in two
versions, the ST16C552 and the ST16C552A. The
552A provides a active low (logic 0) interrupt for the
printer port (INTP) while the 552 provides an active
high (logic 1) INTP interrupt. Additionally, the 552A
does not support the power down feature.
The 552/552A is capable of operation to 1.5Mbps with
a 24 MHz external clock input. With an external clock
input of 1.8432 MHz the user can select data rates up
to 115.2 Kbps.
