DS3904U-020+

DS3904/DS3905
Triple 128-Position Nonvolatile Digital
Variable Resistor/Switch
10 _____________________________________________________________________
one clock pulse per bit of data. Figures 2 and 3
detail how data transfer is accomplished on the 2-
wire bus. Depending upon the state of the R/W bit,
two types of data transfer are possible.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between start and stop
conditions is not limited and is determined by the
master device. The information is transferred byte-
wise and each receiver acknowledges with a ninth
bit.
Within the bus specifications, a regular mode
(100kHz clock rate) and a fast mode (400kHz clock
rate) are defined. The DS3904/DS3905 work in both
modes.
Acknowledge: Each receiving device, when
addressed, generates an acknowledge after the
byte has been received. The master device must
generate an extra clock pulse that is associated
with this acknowledge bit.
A device that acknowledges must pull down the
SDA line during the acknowledge clock pulse in
such a way that the SDA line is a stable low during
the high period of the acknowledge-related clock
pulse. Of course, setup and hold times must be
taken into account. A master must signal an end of
data to the slave by not generating an acknowl-
edge bit on the last byte that has been clocked out
of the slave. In this case, the slave must leave the
data line high to enable the master to generate the
stop condition.
Data transfer from a master transmitter to a
slave receiver. The first byte transmitted by the
master is the command/control byte. Next follows a
number of data bytes. The slave returns an
acknowledge bit after each received byte.
Data transfer from a slave transmitter to a mas-
ter receiver. The master transmits the first byte (the
command/control byte) to the slave. The slave then
returns an acknowledge bit. Next follows the data
byte transmitted by the slave to the master. The
master returns NACK followed by a stop.
The master device generates all serial clock pulses
and the start and stop conditions. A transfer is
ended with a stop condition or with a repeated start
condition. Since a repeated start condition is also
the beginning of the next serial transfer, the bus is
not released.
1
MSB
START
LSB
COMMAND BYTE
*DS3904, USE 0's INSTEAD OF A2 AND A1 FOR THE DEVICE ADDRESS
DEVICE IDENTIFIER
OR
"FAMILY CODE"
SLAVE
ADDRESS
0 1 0 A2* A1* A0 R/W
MSB LSB
DATA BYTE
RHIZ
CONTROL BIT
RESISTOR SETTING
Figure 4. Command and Data Byte Structures
MSB A0h
A0h
A0h
A0h
A1h
F8h
F9h
FAh
00h
80h
7Fh
F9h
LSB
10 010 00START
MSB LSB
111
ACK ACK
11000
MSB LSB
010 010 00START
MSB LSB
111ACK
STOP
ACK
11001
MSB LSB
010 010 00START
MSB LSB
111ACK
STOP
ACK
11010
MSB LSB
10 010 00START
MSB LSB
111
ACK ACK
11001
READ RESISTOR 1 VALUE
A0 = GND FOR DS3904
A0, A1, A2 = GND FOR DS3905
WRITE RESISTOR 0
TO MIN POSITION
MSB LSB
10 010 00
REPEATED
START
MSB LSB
ACK
STOPNACK
FROM
SLAVE
FROM
SLAVE
FROM
SLAVE
MASTER
0
0
1
STOP
MSB LSB
000
ACK
00000
MSB LSB
100
ACK
00000
MSB LSB
011
ACK
11111
SET RESISTOR 1 TO Hi-Z
WRITE RESISTOR 2 TO
MAX POSITION
EXAMPLE 2-WIRE TRANSACTIONS
RESISTOR DATA
Figure 5. Example 2-Wire Transactions
DS3904/DS3905
Triple 128-Position Nonvolatile Digital
Variable Resistor/Switch
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
11
© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
The DS3904/DS3905 can operate in the following three
modes:
1) Slave Receiver Mode: Serial data and clock are
received through SDA and SCL, respectively. After
each byte is received, an acknowledge bit is trans-
mitted. Start and stop conditions are recognized as
the beginning and end of a serial transfer. Address
recognition is performed by hardware after the
slave (device) address and direction bit has been
received.
2) Slave Transmitter Mode: The first byte is received
and handled as in the slave receiver mode.
However, in this mode the direction bit indicates
that the transfer direction is reversed. Serial data is
transmitted on SDA by the DS3904/DS3905 while
the serial clock is input on SCL. Start and stop con-
ditions are recognized as the beginning and end of
a serial transfer.
3) Slave Address: The command/control byte is the
first byte received following the start condition from
the master device. The command/control byte con-
sists of a 4-bit device identifier. For the DS3904, the
identifier is followed by the device-select bits 0, 0,
and A0. For the DS3905, the identifier is followed by
the device-select bits A2, A1, A0. The device identi-
fier is used by the master device to select which
device is to be accessed. When reading or writing
the DS3904/DS3905, the device-select bits must
match the device-select pin(s). The last bit of the
command/control byte (R/W) defines the operation
to be performed. When set to a ‘1’, a read operation
is selected, and when set to a ‘0’, a write operation
is selected.
Following the start condition, the DS3904/DS3905 moni-
tor the SDA bus checking the device-type identifier
being transmitted. Upon receiving the control code, the
appropriate device address bit, and the read/write bit,
the slave device outputs an acknowledge signal on the
SDA line.
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS3904/
DS3905, decouple the power supply with a 0.01µF or
0.1µF capacitor. Use a high-quality ceramic surface-
mount capacitor. Surface-mount components minimize
lead inductance, which improves performance, and
ceramic capacitors tend to have adequate high-fre-
quency response for decoupling applications.
High Resistor Terminal Voltage
It is possible to have a voltage on the resistor-high termi-
nals that is higher than the voltage connected to V
CC
.
For instance, connecting V
CC
to 3.0V while one or more
of the resistor high terminals are connected to 5.0V
allows a 3V system to control a 5V system. The 5.5V
maximum still applies to the limit on the resistor high ter-
minals regardless of the voltage present on V
CC
.
Package Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.

DS3904U-020+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital Potentiometer ICs Triple 128-Position Nonvolatile
Lifecycle:
New from this manufacturer.
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