DS3904/DS3905
Triple 128-Position Nonvolatile Digital
Variable Resistor/Switch
4 ______________________________________________________________________
Note 1: All voltages are referenced to ground.
Note 2: Applies to A0, SDA, SCL for the DS3904 and A0, A1, A2, SDA, SCL for the DS3905. Also applies to H0, H1,
H2 for both DS3904 and DS3905 when in the high-impedance state.
Note 3: I
STBY
specified with SDA = SCL = V
CC
and A0 = GND.
Note 4: Absolute linearity is used to determine expected resistance. Absolute linearity is defined as the deviation
from the straight line drawn from the value of the resistance at position 00h to the value of the resistance at
position 7Fh.
Note 5: Relative linearity is used to determine the change of resistance between two adjacent resistor positions.
Note 6: Temperature coefficient specifies the change in resistance as a function of temperature. The temperature
coefficient varies with resistor position. Limits are guaranteed by design.
Note 7: A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
> 250ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line t
RMAX
+ t
SU:DAT
= 1000ns + 250ns =1250ns before the SCL line is released.
Note 8: After this period, the first clock pulse is generated.
Note 9: The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the SCL
signal.
Note 10: C
B
—total capacitance of one bus line in picofarads, timing referenced to 0.9 x V
CC
and 0.1 x V
CC
.
Note 11: EEPROM write begins after a stop condition occurs.
NONVOLATILE MEMORY CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T
A
= +70°C.)
