DS3904/DS3905
Triple 128-Position Nonvolatile Digital
Variable Resistor/Switch
8 ______________________________________________________________________
Bus Reset
After any interruption in protocol, power loss, or system
reset, the following steps reset the DS3904/DS3905:
1) Clock up to nine cycles.
2) Look for SDA high in each cycle while SCL is high.
3) Create a start condition while SDA is high.
Device Addressing
The DS3904/DS3905 must receive an 8-bit device
address byte following a start condition to enable a
specific device for a read or write operation. The
address byte is clocked into the DS3904/DS3905 MSB
to LSB. For the DS3904, the address byte consists of
101000 binary followed by A0 then the R/W bit. If the
R/W bit is high, a read operation is initiated. For the
DS3905, the address byte consists of 1010 binary fol-
lowed by A2, A1, A0 then the R/W bit. If the R/W bit is
low, a write operation is initiated. For a device to
become active, the value of the address bits must be
the same as the hard-wired address pins on the
DS3904/DS3905. Upon a match of written and hard-
wired addresses, the DS3904/DS3905 output a zero for
one clock cycle as an acknowledge. If the address
does not match, the DS3904/DS3905 return to a low-
power mode.
Write Operations
After receiving a matching device address byte with the
R/W bit set low, the device goes into the write mode of
operation. The master must transmit an 8-bit EEPROM
memory address to the device to define the address
where the data is to be written. After the byte has been
received, the DS3904/DS3905 transmit a zero for one
clock cycle to acknowledge that the memory address
has been received. The master must then transmit an 8-
bit data word to be written into this memory address. The
DS3904/DS3905 again transmit a zero for one clock
cycle to acknowledge the receipt of the data byte. At this
point, the master must terminate the write operation with
a stop condition. The DS3904/DS3905 then enter an
internally timed write process t
w
to the EEPROM memo-
ry. All inputs are disabled during this write cycle.
Acknowledge Polling
Once a EEPROM write is initiated, the part will not
acknowledge until the cycle is complete. Another
option is to wait the maximum write cycle delay before
initiating another write cycle.
Read Operations
After receiving a matching address byte with the R/W bit
set high, the device goes into the read mode of opera-
tion. A read requires a dummy byte write sequence to
load in the register address. Once the device address
and data address bytes are clocked in by the master,
and acknowledged by the DS3904/ DS3905, the master
must generate another start condition (repeated start).
The master now initiates a read by sending the device
address with the R/W bit set high. The DS3904/DS3905
acknowledge the device address and serially clock out
the data byte. The master responds with a NACK and
generates a stop condition afterwards.
See Figures 4 and 5 for command and data byte struc-
tures as well as read and write examples.
2-Wire Serial Port Operation
The 2-wire serial port interface supports a bidirectional
data transmission protocol with device addressing. A
device that sends data on the bus is defined as a trans-
mitter, and a device receiving data as a receiver. The
device that controls the message is called a master. The
devices that are controlled by the master are slaves. The
bus must be controlled by a master device that gener-
ates the SCL, controls the bus access, and generates
the start and stop conditions. The DS3904/DS3905 oper-
ate as slaves on the 2-wire bus. Connections to the bus
are made through SCL and open-drain SDA lines. The
following I/O terminals control the 2-wire serial port: SDA,
SCL, and A0. The DS3905 uses two additional address
pins A1 and A2 to control the 2-wire serial port. Timing
diagrams for the 2-wire serial port can be found in
Figures 2 and 3. Timing information for the 2-wire serial
port is provided in the
AC Electrical Characteristics
table
for 2-wire serial communications.
