LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 2 June 2009 4 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
5. Pinning information
5.1 Pinning
Fig 2. Pin configuration (LQFP48)
LPC2101FBD48
LPC2102FBD48
LPC2103FBD48
P0.19/MAT1.2/MISO1 P0.11/CTS1/CAP1.1/AD0.4
P0.20/MAT1.3/MOSI1 P0.10/RTS1/CAP1.0/AD0.3
P0.21/SSEL1/MAT3.0 P0.24/AD0.2
VBAT P0.23/AD0.1
V
DD(1V8)
P0.22/AD0.0
RST V
SSA
V
SS
P0.9/RXD1/MAT2.2
P0.27/TRST/CAP2.0 P0.8/TXD1/MAT2.1
P0.28/TMS/CAP2.1 P0.7/SSEL0/MAT2.0
P0.29/TCK/CAP2.2 DBGSEL
XTAL1 RTCK
XTAL2 RTCX2
P0.0/TXD0/MAT3.1 P0.18/CAP1.3/SDA1
P0.1/RXD0/MAT3.2 P0.17/CAP1.2/SCL1
P0.30/TDI/MAT3.3 P0.16/EINT0/MAT0.2
P0.31/TDO P0.15/RI1/EINT2
V
DD(3V3)
P0.14/DCD1/SCK1/EINT1
P0.2/SCL0/CAP0.0 V
SS
V
SS
V
DDA
RTCX1 P0.13/DTR1/MAT1.1
P0.3/SDA0/MAT0.0 V
DD(3V3)
P0.4/SCK0/CAP0.1 P0.26/AD0.7
P0.5/MISO0/MAT0.1
P0.6/MOSI0/CAP0.2
P0.25/AD0.6
P0.12/DSR1/MAT1.0/AD0.5
002aab821
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
48
47
46
45
44
43
42
41
40
39
38
37
24
LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 2 June 2009 5 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
Fig 3. Pin configuration (HVQFN48)
002aad918
LPC2102FHN48
LPC2103FHN48
LPC2103FHN48H
Transparent top view
12 25
11 26
10 27
9 28
8 29
7 30
6 31
5 32
4 33
3 34
2 35
1 36
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
terminal 1
index area
P0.19/MAT1.2/MISO1
P0.20/MAT1.3/MOSI1
P0.21/SSEL1/MAT3.0
VBAT
V
DD(1V8)
RST
V
SS
P0.27/TRST/CAP2.0
P0.28/TMS/CAP2.1
P0.29/TCK/CAP2.2
XTAL1
XTAL2
P0.18/CAP1.3/SDA1
P0.17/CAP1.2/SCL1
P0.16/EINT0/MAT0.2
P0.15/RI1/EINT2
P0.14/DCD1/SCK1/EINT1
V
SS
V
DDA
P0.13/DTR1/MAT1.1
V
DD(3V3)
P0.26/AD0.7
P0.25/AD0.6
P0.12/DSR1/MAT1.0/AD0.5
P0.11/CTS1/CAP1.1/AD0.4
P0.10/RTS1/CAP1.0/AD0.3
P0.24/AD0.2
P0.23/AD0.1
P0.22/AD0.0
V
SSA
P0.9/RXD1/MAT2.2
P0.8/TXD1/MAT2.1
P0.7/SSEL0/MAT2.0
DBGSEL
RTCK
RTCX2
P0.0/TXD0/MAT3.1
P0.1/RXD0/MAT3.2
P0.30/TDI/MAT3.3
P0.31/TDO
V
DD(3V3)
P0.2/SCL0/CAP0.0
V
SS
RTCX1
P0.3/SDA0/MAT0.0
P0.4/SCK0/CAP0.1
P0.5/MISO0/MAT0.1
P0.6/MOSI0/CAP0.2
LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 2 June 2009 6 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
5.2 Pin description
Table 3. Pin description
Symbol Pin Type Description
P0.0 to P0.31 I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit.
A total of 31 pins of the Port 0 can be used as general purpose bidirectional
digital I/Os while P0.31 is an output only pin. The operation of port 0 pins
depends upon the pin function selected via the pin connect block.
P0.0/TXD0/
MAT3.1
13
[1]
I/O P0.0 — General purpose input/output digital pin.
O TXD0 — Transmitter output for UART0.
O MAT3.1 — PWM output 1 for Timer 3.
P0.1/RXD0/
MAT3.2
14
[1]
I/O P0.1 — General purpose input/output digital pin.
I RXD0 — Receiver input for UART0.
O MAT3.2 — PWM output 2 for Timer 3.
P0.2/SCL0/
CAP0.0
18
[2]
I/O P0.2 — General purpose input/output digital pin. Output is open-drain.
I/O SCL0 — I
2
C0 clock Input/output. Open-drain output (for I
2
C-bus compliance).
I CAP0.0 — Capture input for Timer 0, channel 0.
P0.3/SDA0/
MAT0.0
21
[2]
I/O P0.3 — General purpose input/output digital pin. Output is open-drain.
I/O SDA0 — I
2
C0 data input/output. Open-drain output (for I
2
C-bus compliance).
O MAT0.0 — PWM output for Timer 0, channel 0. Output is open-drain.
P0.4/SCK0/
CAP0.1
22
[1]
I/O P0.4 — General purpose input/output digital pin.
I/O SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.
I CAP0.1 — Capture input for Timer 0, channel 1.
P0.5/MISO0/
MAT0.1
23
[1]
I/O P0.5 — General purpose input/output digital pin.
I/O MISO0 — Master In Slave Out for SPI0. Data input to SPI master or data
output from SPI slave.
O MAT0.1 — PWM output for Timer 0, channel 1.
P0.6/MOSI0/
CAP0.2
24
[1]
I/O P0.6 — General purpose input/output digital pin.
I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data
input to SPI slave.
I CAP0.2 — Capture input for Timer 0, channel 2.
P0.7/SSEL0/
MAT2.0
28
[1]
I/O P0.7 — General purpose input/output digital pin.
I SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.
O MAT2.0 — PWM output for Timer 2, channel 0.
P0.8/TXD1/
MAT2.1
29
[1]
I/O P0.8 — General purpose input/output digital pin.
O TXD1 — Transmitter output for UART1.
O MAT2.1 — PWM output for Timer 2, channel 1.
P0.9/RXD1/
MAT2.2
30
[1]
I/O P0.9 — General purpose input/output digital pin.
I RXD1 — Receiver input for UART1.
O MAT2.2 — PWM output for Timer 2, channel 2.
P0.10/RTS1/
CAP1.0/AD0.3
35
[3]
I/O P0.10 — General purpose input/output digital pin.
O RTS1 — Request to Send output for UART1.
I CAP1.0 — Capture input for Timer 1, channel 0.
I AD0.3 — ADC 0, input 3.

LPC2103FBD48,151

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU ARM7 32KF/8KR/10BADC
Lifecycle:
New from this manufacturer.
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