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8344BYLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
Low Skew, 1-TO-24 Differential-to
LVCMOS Fanout Buffer
8344
DATASHEET
8344 REVISION A 3/24/15 1 ©2015 Integrated Device Technology, Inc.
GENERAL DESCRIPTION
The 8344 is a low voltage, low skew, 1-to-24 Differential-to-LVCMOS
Fanout Buffer. The 8344 is designed to translate any differential
signal levels to LVCMOS levels. The low impedance LVCMOS
outputs are designed to drive 50Ω series or parallel terminated
transmission lines. The effective fanout can be increased to 48
by utilizing the ability of the outputs to drive two series terminated
lines. Redundant clock applications can make use of the dual clock
input. The dual clock inputs also facilitate board level testing. 8344
is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V
output operating supply modes.
Guaranteed output and part-to-part skew characteristics make the
8344 ideal for those clock distribution applications demanding well
defi ned performance and repeatability.
FEATURES
• Twenty-four LVCMOS outputs, 7Ω typical output impedance
• Selectable differential clock input pairs for redundant
clock applications
• CLKx, nCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 167MHz
• Translates any differential input signal (LVPECL, LVHSTL,
LVDS) to LVCMOS without external bias networks
• Translates any single-ended input signal to LVCMOS
with resistor bias on nCLK input
• Multiple output enable pins for disabling unused outputs
in reduced fanout applications
• Output skew: 275ps (maximum)
• Part-to-part skew: 600ps (maximum)
• Bank skew: 150ps (maximum)
• Propagation Delay: 4.3ns (maximum)
• 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
BLOCK DIAGRAM PIN ASSIGNMENT
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
8344 DATA SHEET
2 REVISION A 3/24/15
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
Number Name Type
Description
1, 2, 5, 6
7, 8, 11, 12
Q16, Q17, Q18, Q19
Q20, Q21, Q22, Q23
Output
Q15 thru Q23 outputs. 7Ω typical output impedance.
3, 9, 28,
34, 39, 45
V
DDO
Power
Output supply pins. Connect 3.3V or 2.5V.
4, 10, 14,18,
27, 33, 40, 46
GND Power
Power supply ground. Connect to ground.
13 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects CLK1, nCLK1 inputs.
When LOW, selects CLK0, nCLK0 inputs.
15, 19 V
DD
Power
Positive supply pins. Connect 3.3V or 2.5V.
16 nCLK1 Input Pullup
Inverting input of secondary differential clock input pair.
17 CLK1 Input Pulldown
Non-inverting input of secondary differential clock input pair.
20 nCLK0 Input Pullup
Inverting input of primary differential clock input pair.
21 CLK0 Input Pulldown
Non-inverting input of primary differential clock input pair.
22 OE3 Input Pullup
Output enable. Controls enabling and disabling of outputs
Q16 thru Q23.
23 OE2 Input Pullup
Output enable. Controls enabling and disabling of outputs
Q8 thru Q15.
24 OE1 Input Pullup
Output enable. Controls enabling and disabling of outputs
Q0 thru Q7.
25, 26, 29, 30
31, 32, 35, 36
Q0, Q1, Q2, Q3
Q4, Q5, Q6, Q7
Output Q0 thru Q7 outputs. 7Ω typical output impedance.
37, 38, 41, 42
43, 44, 47, 48
Q8, Q9, Q10, Q11
Q12, Q13, Q14, Q15
Output Q8 thru Q15 outputs. 7Ω typical output impedance.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
C
PD
Power Dissipation Capacitance
(per output)
V
DD
, V
DDO
= 3.465V pF
V
DD
= 3.465V, V
DDO
= 2.625V pF
V
DD
, V
DDO
= 2.625V pF
R
PULLUP
Input Pullup Resistor 51 kΩ
R
PULLDOWN
Input Pulldown Resistor 51 kΩ
R
OUT
Output Impedance 7 Ω
REVISION A 3/24/15
ICS8344 DATA SHEET
3 LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
TABLE 3B. CLOCK SELECT FUNCTION TABLE
TABLE 3C. CLOCK INPUTS FUNCTION TABLE
Bank 1 Bank 2 Bank 3
Input Output Input Output Input Output
OE1 Q0-Q7 OE2 Q8-Q15 OE3 Q16-Q23
0 Hi-Z 0 Hi-Z 0 Hi-Z
1 Active 1 Active 1 Active
Control Input Clock
CLK_SEL CLK0, nCLK0 CLK1, nCLK1
0 Selected De-selected
1 De-selected Selected
Inputs Outputs
Input to Output Mode Polarity
OE1, OE2, OE3 CLK nCLK Q0 thru Q23
1 0 1 LOW Differential to Single Ended Non Inverting
1 1 0 HIGH Differential to Single Ended Non Inverting
1 0 Biased; NOTE 1 LOW Single Ended to Differential Non Inverting
1 1 Biased; NOTE 1 HIGH Single Ended to Differential Non Inverting
1 Biased; NOTE 1 0 HIGH Single Ended to Differential Inverting
1 Biased; NOTE 1 1 LOW Single Ended to Differential Inverting
NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

8344BYLFT

Mfr. #:
Buy 8344BYLFT
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 24 LVCMOS OUT BUFFER
Lifecycle:
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