8344BYLFT Datasheet 8344BYLFT, 8344BYLF | P13-P15

REVISION A 3/24/15

ICS8344 DATA SHEET

13 LOW SKEW, 1-TO-24

DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER

APPLICATION INFORMATION

Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V

/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V

= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.

FIGURE 1 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

LOW SKEW, 1-TO-24

DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER

8344 DATA SHEET

14 REVISION A 3/24/15

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for 8344 is: 1449

TABLE 6. θ

VS. AIR FLOW TABLE

by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W

NOTE: For 48-pin LQFP

REVISION A 3/24/15

ICS8344 DATA SHEET

15 LOW SKEW, 1-TO-24

DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER

PACKAGE OUTLINE - Y SUFFIX

TABLE 7. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MS-026

JEDEC VARIATION

ALL DIMENSIONS IN MILLIMETERS

SYMBOL

BBC

MINIMUM NOMINAL MAXIMUM

-- -- 1.60

0.05 -- 0.15

1.35 1.40 1.45

0.17 0.22 0.27

0.09 -- 0.20

9.00 BASIC

7.00 BASIC

5.50 Ref.

9.00 BASIC

7.00 BASIC

5.50 Ref.

0.50 BASIC

0.45 0.60 0.75

0°

7°

ccc

-- -- 0.08

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

8344BYLFT

Mfr. #:

Buy 8344BYLFT

Manufacturer:

IDT

Description:

Clock Drivers & Distribution 24 LVCMOS OUT BUFFER

Lifecycle:

New from this manufacturer.

Delivery:

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8344BYLFT

8344BYLFT

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