22
LTC1436A
LTC1436-PLL-A/LTC1437A
14367afb
APPLICATIONS INFORMATION
WUU
U
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately 25(C
LOAD
).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
Automotive Considerations: Plugging into the
Cigarette Lighter
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation.
But before you connect, be advised: you are plugging into
the supply from hell. The main battery line in an automo-
bile is the source of a number of nasty potential transients,
including load dump, reverse battery, and double battery.
Load dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse battery is
just what it says, while double battery is a consequence of
tow-truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
The network shown in Figure 14 is the most straightfor-
ward approach to protect a DC/DC converter from the
ravages of an automotive battery line. The series diode
prevents current from flowing during reverse battery,
while the transient suppressor clamps the input voltage
during load dump. Note that the transient suppressor
should not conduct during double battery operation, but
must still clamp the input voltage below breakdown of the
converter. Although the LTC1436A/LTC1437A have a maxi-
mum input voltage of 36V, most applications will be
limited to 30V by the MOSFET BV
DSS
.
Design Example
As a design example, assume V
IN
= 12V (nominal), V
IN
=
22V (max), V
OUT
= 1.6V, I
MAX
= 3A and f = 250kHz, R
SENSE
and C
OSC
can immediately be calculated:
R
mV
A
CpF
SENSE
OSC
==
=
=
100
3
0 033
13710
250
11 43
4
.
.( )
Refering to Figure 3, a 4.7µH inductor falls within the
recommended range. To check the actual value of the
ripple current the following equation is used:
I
V
fL
V
V
L
OUT OUT
IN
=
()( )
1
The highest value of the ripple current occurs at the
maximum input voltage:
CpF
Frequency kHz
OSC
()
=
()
13710
11
4
.( )
The lowest duty cycle also occurs at maximum input
voltage. The on-time during this condition should be
checked to make sure it doesn’t violate the LTC1436A/
LTC1437A’s minimum on-time and cause cycle skipping
to occur. The required on-time at V
IN(MAX)
is:
t
V
Vf
V
V kHz
ns
ON MIN
OUT
IN MAX
()
()
.
=
()
()
=
()( )
=
16
22 250
291
The I
L
was previously calculated to be 1.3A, which is
43% of I
MAX
. From Figure 12, the LTC1436A/LTC1437A’s
minimum on-time at 43% ripple is about 235ns. There-
fore, the minimum on-time is sufficient and no cycle
skipping will occur.
Figure 14. Automotive Application Protection
1436 F14
50A I
PK
RATING
LTC1436A
LTC1437A
TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT
1.5KA24A
V
IN
12V
23
LTC1436A
LTC1436A-PLL/LTC1437A
14367afb
APPLICATIONS INFORMATION
WUU
U
The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Siliconix Si4412DY results
in: R
DS(ON)
= 0.042, C
RSS
= 100pF. At maximum input
voltage with T (estimated) = 50°C:
P
V
V
CC
V A pF kHz mW
MAIN
=
()
+
()
° °
()
[]
()
+
()()( )( )
=
16
22
3 1 0 005 50 25 0 042
2 5 22 3 100 250 88
2
185
.
..
.
.
The most stringent requirement for the synchronous
N-channel MOSFET occurs when V
OUT
= 0 (i.e. short
circuit). In this case the worst-case dissipation rises to:
PI R
SYNC SC AVG DS ON
=
+
()
(
)
(
)
2
1 δ
With the 0.033 sense resistor I
SC(AVG)
= 4A will result,
increasing the Si4412DY dissipation to 950mW at a die
temperature of 105°C.
C
IN
is chosen for an RMS current rating of at least 1.5A at
temperature. C
OUT
is chosen with an ESR of 0.03 for low
output ripple. The output ripple in continuous mode will be
highest at the maximum input voltage. The output voltage
ripple due to ESR is approximately:
VRI AmV
ORIPPLE ESR L
=
()
=
()
=∆Ω003 13 39..
P-P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1436A/LTC1437A. These items are also illustrated
graphically in the layout diagram of Figure 15. Check the
following in your layout:
1. Are the signal and power grounds segregated? The
LTC1436A/LTC1437A signal ground pin must return to
the (–) plate of C
OUT
. The power ground connects to the
source of the bottom N-channel MOSFET, anode of the
Schottky diode, and (–) plate of C
IN
, which should have
as short lead lengths as possible.
2. Does the LTC1436A/LTC1437A V
OSENSE
pin connect to
the (+) plate of C
OUT
? In adjustable applications, the
resistive divider R1/R2 must be connected between the
(+) plate of C
OUT
and signal ground. The 100pF capaci-
tor should be as close as possible to the LTC1436A/
LTC1437A.
3. Are the SENSE
and SENSE
+
leads routed together with
minimum PC trace spacing? The filter capacitor be-
tween SENSE
+
and SENSE
should be as close as
possible to the LTC1436A/LTC1437A.
4. Does the (+) plate of C
IN
connect to the drain of the
topside MOSFET(s) as closely as possible? This capaci-
tor provides the AC current to the MOSFET(s).
5. Is the INTV
CC
decoupling capacitor connected closely
between
INTV
CC
and the power ground pin? This ca-
pacitor carries the MOSFET driver peak currents.
6. Keep the switching node SW away from sensitive small-
signal nodes. Ideally, the switch node should be placed
at the furthest point from the LTC1436A/LTC1437A.
7. Route the PLLIN line away from Boost and SW pins to
avoid unwanted pickup (Boost and SW pins have high
dV/dTs).
8. SGND should be used exclusively for grounding exter-
nal components on PLL LPF, C
OSC
, I
TH
, LBI, SFB,
V
OSENSE
and AUXFB pins.
9. If operating close to the minimum on-time limit, is the
sense resistor oriented on the radial axis of the induc-
tor? See Figure 13.
24
LTC1436A
LTC1436-PLL-A/LTC1437A
14367afb
TYPICAL APPLICATIONS
U
Intel Mobile CPU VID Core Power Converter with 1.8V I/O Supply
+
+
+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PLL LPF
C
OSC
RUN/SS
LBO
LBI
I
TH
SFB
SGND
V
PROG
V
OSENSE
NC
SENSE
SENSE
+
AUXON
PLLIN
POR
BOOST
TGL
SW
TGS
V
IN
INTV
CC
DRV
CC
BG
PGND
EXTV
CC
AUXDR
AUXFB
R
LP
R
C
C
LP
C
C
1000pF
OPEN
100pF
R1
C
OUT
R
SENSE
L1
4.7µF
C
B
0.1µF
D
B
M3
D1
EXT CLOCK
LTC1437A
+
+
M1
M2
1437 F15
C
IN
R2
OUTPUT DIVIDER
REQUIRED WITH
V
PRGM
OPEN
BOLD LINES INDICATE
HIGH CURRENT PATHS
5V EXT V
CC
CONNECTION
AUX
ON/OFF
C
SS
C
C2
C
OSC
V
IN
V
OUT
Figure 15. LTC1437A Layout Diagram
APPLICATIONS INFORMATION
WUU
U
1436 TA09
+
+
C
C
220pF
100pF
R
C
10k
C
SS
0.1µF
C
OSC
43pF
1000pF
AUX
ON/OFF
L1
3.3µH
R
SENSE
0.015
V
IN
4.5V TO 22V
V
CORE
1.3V TO 2V
7A
V
IN2
3.3V
SGND
(PIN 6)
0.22µF
0.1µF
10k
C
IN
22µF
35V
X2
4.7µF
M1
Si4410DY
M2
Si4410DY
*D
B
D1
MBRS140T3
C
C2
1000pF
4.7
+
C
OUT
820µF
4V
× 2
V
CC
FB
0 12
VID
LTC1706-19
FROM µP
3
7
36
5
812 4
GND
SENSE
V
IN
2
3
4
7
6
8
INTV
CC
C
OSC
EXTERNAL
FREQUENCY
SYNCHRONIZATION
SGND
V
PROG
PLL LPF PLLIN
V
OSENSE
TGL
TGS
SW
AUXDR
PGND
BG
BOOST
RUN/SS
I
TH
SENSE
+
AUXON
AUXFB
SENSE
LTC1436A-PLL
V
I/O
1.8V
150mA
M3
IRLML2803
18
124
0.1µF
21
19
20
17
22
16
15
13
9
10
11
12
47k
10.5k
20k
51pF
MMBT2907L
47µF
4V**
*CMDSH-3
**INPUT CAPACITOR MAY NOT BE NECESSARY IF
3.3V SUPPLY HAS SUFFICIENT CAPACITANCE
47µF
4V

LTC1436ACGN-PLL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
IC REG CTRLR BUCK 24SSOP
Lifecycle:
New from this manufacturer.
Delivery:
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