REV. D
AD8001
–12–
Communications
Distortion is a key specification in communications applications.
Intermodulation distortion (IMD) is a measure of the ability of
an amplifier to pass complex signals without the generation of
spurious harmonics. The third order products are usually the
most problematic since several of them fall near the fundamentals
and do not lend themselves to filtering. Theory predicts that the
third order harmonic distortion components increase in power at
three times the rate of the fundamental tones. The specification
of third order intercept as the virtual point where fundamental and
harmonic power are equal is one standard measure of distortion
performance. Op amps used in closed-loop applications do not
always obey this simple theory. At a gain of +2, the AD8001
has performance summarized in Figure 10. Here the worst third
order products are plotted versus input power. The third order
intercept of the AD8001 is +33 dBm at 10 MHz.
–80
3–7
–75
210–4–5 6–2
–70
–65
–60
–55
–50
–45
–1
THIRD ORDER IMD – dBc
INPUT POWER – dBm
–6–8 4 5–3
2F
2
– F
1
2F
1
– F
2
G = +2
F
1
= 10MHz
F
2
= 12MHz
Figure 10. Third Order IMD; F
1
= 10 MHz, F
2
= 12 MHz
Operation as a Video Line Driver
The AD8001 has been designed to offer outstanding perfor-
mance as a video line driver. The important specifications of
differential gain (0.01%) and differential phase (0.025°) meet
the most exacting HDTV demands for driving one video load.
The AD8001 also drives up to two back terminated loads as
shown in Figure 11, with equally impressive performance (0.01%,
0.07°). Another important consideration is isolation between
loads in a multiple load application. The AD8001 has more
than 40 dB of isolation at 5 MHz when driving two 75 back
terminated loads.
909909
75
CABLE
75
75
V
OUT
NO. 1
V
OUT
NO. 2
+V
S
–V
S
V
IN
0.1F
0.001F
AD8001
0.1F
75
CABLE
75
75
75
CABLE
+
0.001F
75
Figure 11. Video Line Driver
REV. D
AD8001
–13–
0.1F
+V
S
–V
S
20
50
1k
18
17
16
15
14
13
12
11
–V
REF A
10pF
CLOCK
5, 9, 22,
24, 37, 41
4,19, 21 25, 27, 42
0.1F
38
8
–V
REF B
6
+V
INT
2
3
+V
REF A
A
IN A
649
324ANALOG
IN A
0.5V
1.3k
AD707
43
+V
REF B
20k
0.1F
–2V
1.3k
20k
649
ANALOG
IN B
0.5V
324
20
0.1F
40
COMP
1
A
IN B
ENCODE A ENCODE B
10
36
ENCODE
74ACT04
0.1F
+5V
28
29
30
31
32
33
34
35
RZ1
RZ2
D
0A
(LSB)
D
7A
(MSB)
D
0B
(LSB)
D
7B
(MSB)
7, 20,
26, 39
–5V
1N4001
AD9058
(J-LEAD)
RZ1, RZ2 = 2,000 SIP (8-PKG)
74ACT 273
74ACT 273
8
8
AD8001
AD8001
Figure 12. AD8001 Driving a Dual A-to-D Converter
Driving A-to-D Converters
The AD8001 is well suited for driving high speed analog-to-
digital converters such as the AD9058. The AD9058 is a dual
8-bit 50 MSPS ADC. In the circuit below, the AD8001 is
shown driving the inputs of the AD9058, which are configured
for 0 V to 2 V ranges. Bipolar input signals are buffered, amplified
(–2×), and offset (by +1.0 V) into the proper input range of the
ADC. Using the AD9058’s internal +2 V reference connected
to both ADCs as shown in Figure 12 reduces the number of
external components required to create a complete data
acquisition system. The 20 resistors in series with ADC inputs
are used to help the AD8001s drive the 10 pF ADC input
capacitance. The AD8001 only adds 100 mW to the power
consumption while not limiting the performance of the circuit.
REV. D
AD8001
–14–
Layout Considerations
The specified high speed performance of the AD8001 requires
careful attention to board layout and component selection. Proper
R
F
design techniques and low parasitic component selection
are mandatory.
The PCB should have a ground plane covering all unused portions
of the component side of the board to provide a low impedance
ground path. The ground plane should be removed from the area
near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see Figure 13).
One end should be connected to the ground plane and the other
within 1/8 inch of each power pin. An additional large
(4.7 µF–10 µF) tantalum electrolytic capacitor should be con-
nected in parallel, but not necessarily so close, to supply current
for fast, large-signal changes at the output.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the invert-
ing input will significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50 or 75 and be properly termi-
nated at each end.
Inverting Configuration Supply Bypassing
C1
0.1F
C2
0.1F
+V
S
–V
S
C3
10F
C4
10F
Noninverting Configuration
R
F
R
O
IN
+V
S
–V
S
R
S
R
T
R
G
OUT
R
F
R
O
IN
+V
S
–V
S
R
T
R
G
OUT
Figure 13. Inverting and Noninverting Configurations for Evaluation Boards
Table I. Recommended Component Values
AD8001AN (PDIP) AD8001AR (SOIC) AD8001ART (SOT-23-5)
Gain Gain Gain
Component –1 +1 +2 +10 +100 –1 +1 +2 +10 +100 –1 +1 +2 +10 +100
R
F
() 649 1050 750 470 1000 604 953 681 470 1000 845 1000 768 470 1000
R
G
() 649 750 51 10 604 681 51 10 845 768 51 10
R
O
(Nominal) () 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9
R
S
()0 0 0
R
T
(Nominal) () 54.9 49.9 49.9 49.9 49.9 54.9 49.9 49.9 49.9 49.9 54.9 49.9 49.9 49.9 49.9
Small Signal 340 880 460 260 20 370 710 440 260 20 240 795 380 260 20
BW (MHz)
0.1 dB Flatness 105 70 105 130 100 120 110 300 145
(MHz)

AD8001ARZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Video Amplifiers 800MHz 50mW Current Feedback
Lifecycle:
New from this manufacturer.
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