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STMPE321QTR

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I2C interface STMPE321
10/40 Doc ID 15791 Rev 3
3 I
2
C interface
The following features are supported by the I
2
C interface:
● I
2
C slave device
● Compliance with Philips I
2
C specification version 2.1
● Standard (up to 100 kbps) and fast (up to 400 kbps) modes.
● 7-bit and 10-bit device addressing modes
● General call
● Start/Restart/Stop
● I
2
C address is 0x58 (0xB0/0xB1 for write/read, including the LSB)
Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.
A Start condition must precede any data/command transfer. The device continuously
monitors for a Start condition and does not respond to any transaction unless one is
encountered.
Stop condition
A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state.
A Stop condition terminates communication between the slave device and bus master. A
read command that is followed by NoAck can be followed by a Stop condition to force the
slave device into idle mode. When the slave device is in idle mode, it is ready to receive the
next I
2
C transaction. A Stop condition at the end of a write command stops the write
operation to the registers.
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls
the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave
the SDATA in high state if it does not acknowledge the receipt of the data.
Data Input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA
signal must be stable during the rising edge of SCLK and the SDATA signal must change
only when SCLK is driven low.
Memory addressing
For the bus master to communicate to the slave device, the bus master must initiate a Start
condition, followed by the slave device address. Accompanying the slave device address,
there is a Read/WRITE
bit (R/W). The bit is set to 1 for a read operation, and 0 for a write
operation.
If a match occurs on the slave device address, the corresponding device gives an
acknowledgement on the SDA during the 9th bit time. If there is no match, it deselects itself
from the bus by not responding to the transaction.
STMPE321 I2C interface
Doc ID 15791 Rev 3 11/40
Table 4. Operation modes
Figure 6. Read and write modes (random and sequential)
Mode Byte Programming sequence
Read ≥1
Start, Device address, R/W
= 0, Register address to be read
Restart, Device address, R/W
= 1, Data Read, STOP
If no Stop is issued, the Data Read can be continuously performed. If
the register address falls within the range that allows an address auto-
increment, then the register address auto-increments internally after
every byte of data being read. For those register addresses that fall
within a non-incremental address range, the address is kept static
throughout the entire write operations. Refer to the memory map table
for the address ranges that are auto and non-increment. An example
of such a non-increment address is FIFO.
Write ≥1
Start, Device address, R/W
= 0, Register address to be written, Data
Write, Stop
If no Stop is issued, the Data Write can be continuously performed. If
the register address falls within the range that allows address auto-
increment, then the register address auto-increments internally after
every byte of data being written in. For those register addresses that
fall within a non-incremental address range, the address is kept static
throughout the entire write operations. Refer to the memory map table
for the address ranges that are auto and non-increment.
Start
R/W=0
Ack
Device
Address
Reg
Address
Ack
Restart
Device
Address
Ack
R/W=1
Data
Read
No Ack
Stop
One byte
Read
Start
R/W=0
Ack
Device
Address
Reg
Address
Ack
Restart
Device
Address
Ack
R/W=1
Data
Read
Ack
More than one byte
Read
Ack
No Ack
Stop
Data
Read + 1
Data
Read + 2
Start
R/W=0
Ack
Device
Address
Reg
Address
Ack
Data
to be
written
Ack
Stop
One byte
Write
More than one byte
Read
Start
R/W=0
Ack
Device
Address
Reg
Address
Ack
Data to
Write
Ack
Stop
Data to
Write + 2
Ack
Ack
Data to
Write + 1
Master
Slave
Register map and function description STMPE321
12/40 Doc ID 15791 Rev 3
4 Register map and function description
This section lists and describes the registers in the STMPE321 device starting with a
register map, and then provides detailed descriptions of the register types.
Table 5. Register summary map table
Address Register name Bit Type Reset value Function
0x00 CHIP_ID_0 8 R 0x03 Device identification
0x01 CHIP_ID_1 8 R 0x21 Device identification
0x02 ID_VER 8 R 0x03 Revision number
0x03 SYS_CFG_1 8 R/W 0x00 System configuration 1
0x04 SYS_CFG_2 8 R/W 0xEF System configuration 2
0x08 INT_CTRL 8 R/W 0x01 Interrupt control register
0x09 INT_EN 8 R/W 0x01 Interrupt enable register
0x0A INT_STA 8 R 0x09 Interrupt status register
0x0B GPIO_INT_EN_lsb 8 R/W 0x00 GPIO interrupt enable register
0x0C GPIO_INT_EN_msb 8 R/W 0x00 GPIO interrupt enable register
0x0D GPIO_INT_STA_lsb 8 R/W 0x00 GPIO interrupt status register
0x0E GPIO_INT_STA_msb 8 R/W 0x00 GPIO interrupt status register
0x10 GPIO_MR 8 R/W 0x00 GPIO monitor pin
0x12 GPIO_SET 8 R/W 0x00 GPIO set pin state register
0x14 GPIO_DIR 8 R/W 0x00 GPIO set pin direction register
0x16 GPIO_FUNCT 8 R/W 0x00 GPIO function register
0x18 TOUCH_FIFO 64 R 0x00 Fifo access for touch data buffer
0x20 FEATURE_SEL 8 R/W 0x04 Feature selection
0x21 ETC_WAIT 8 R/W 0x27 Wait time
0x22 CAL_INTERVAL 8 R/W 0x30 Calibration interval
0x23 INTEGRATION_ TIME 8 R/W 0x0F Integration time
0x25 CTRL 8 R/W 0x00 Control
0x26 INT_MASK 8 R/W 0x08 Interrupt mask
0x27 INT_CLR 8 R/W 0x00 Interrupt clear
0x28 FILTER_PERIOD 8 R/W 0x00 Filter period
0x29 FILTER_THRESHOLD 8 R/W 0x00 Filter threshold
0x2A REF_DLY 8 R/W 0x00 Reference delay
0x30 -
0x32
TVR [0-2] 8 R/W 0x08 Touch variance setting
0x40 EVR 8 R/W 0x04 Environmental variance
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STMPE321QTR

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Buy STMPE321QTR
Manufacturer:
STMicroelectronics
Description:
IC CTLR TOUCH KEY 3CH 12-QFN
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