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STMPE321QTR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
STMPE321 Interrupt controller module
Doc ID 15791 Rev 3 19/40
INT_EN Interrupt enable register
Address: 0x09
Type: R/W
Reset: 0x01
Description: This register is used to enable the interruption from a system related interrupt source
to the host. Writing ‘1’ in this register enables the corresponding interrupt event to
generate interrupt signal at the INT pin. Note that even if the interrupt is not enabled,
an interrupt event is still reflected in the interrupt status register.
76543 2 1 0
GPIO RESERVED GEN FIFO POR
[7] GPIO:
One or more level transition in enabled GPIOs
[6:3] RESERVED
Must be set to ‘0’ at all times.
[2] GEN:
System INT (A2I, I2A, EOC)
[1] FIFO:
Data available in FIFO. This interrupt can be cleared only if FIFO is empty.
[0] POR:
Power-on reset
Interrupt controller module STMPE321
20/40 Doc ID 15791 Rev 3
INT_STA Interrupt status register
Address: 0x0A
Type: R/W
Reset: 0x09
Description: This register is used to enable the interruption from a system related interrupt source
to the host. Regardless of whether or not the IESYSIOR bits are enabled, the
ISSYSIOR bits are still updated. Writing ‘1’ clears a bit in this register. Writing ‘0’ has
no effect.
76543 2 1 0
GPIO RESERVED GEN FIFO POR
[7] GPIO:
One or more level transition in enabled GPIOs
[6:3] RESERVED:
Some of these bits might be set to '1' by hardware during normal operation. The content of
these bit is for internal operation and are not required for normal use of device.
[2] GEN:
System INT (A2I, IA2, EOC)
[1] FIFO:
Data available in FIFO
[0] POR:
Power-on reset
STMPE321 Interrupt controller module
Doc ID 15791 Rev 3 21/40
GPIO_INT_EN GPIO interrupt enable registerI
Address: 0x0B, 0x0C
Type: R/W
Reset: 0x00
Description: The GPIO interrupt enable register is used to enable the interruption from a particular
GPIO interrupt source to the host. The IEg[2:0] bits and the interrupt enable mask bits
correspond to the GPIO[2:0]
pins.
GPIO_INT_STA GPIO interrupt status register
Address: 0x0D, 0x0E
Type: R/W
Reset: 0x00
Description: The GPIO interrupt status register LSB monitors the status of the interruption from a
particular GPIO pin interrupt source to the host. Regardless of whether or not the
IEGPIOR bits are enabled, the INT_STA_GPIO_LSB bits are still updated. The
ISG[2:0] bits are the interrupt status bits correspond to the GPIO[2:0] pins.
76543 2 1 0
RESERVED IEG
[7:3] RESERVED
[2:0] IEG[2:0]
Interrupt enable GPIO mask (where x = 2 to 0)
Writing a ‘1’ to the IE[x] bit enables the interruption to the host.
76543 2 1 0
ISG
[7:0] ISG[x]:
Interrupt status GPIO (where x = 2 to 0)
Read:
Interrupt status of the GPIO[x]. Writing ‘1’ clears a bit. Writing ‘0’ has no effect.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

STMPE321QTR

Mfr. #:
Buy STMPE321QTR
Manufacturer:
STMicroelectronics
Description:
IC CTLR TOUCH KEY 3CH 12-QFN
Lifecycle:
New from this manufacturer.
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