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8T49N366A-999ASGI8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
IDT8T49N366AASGI REVISION A JUNE 28, 2013 10 ©2013 Integrated Device Technology, Inc.
IDT8T49N366I Data Sheet FEMTOCLOCK
®
NG TRIPLE UNIVERSAL FREQUENCY TRANSLATOR
TM
Register Descriptions
Please consult IDT fro configuration software and/or guides to assist
in selection of optimal register settings for the desired configurations.
The below register map applies to each PLL. Register bit names have
‘x’ at the end of the name. This should be replaced by ‘A’, ‘B’ or ‘C’ as
appropriate to the PLL being addressed at the time.
Table 4D. I
2
C Register Map
NOTE: “x” denotes A, B or C.
Reg
Binary
Register
Address
Register Bit
D7 D6 D5 D4 D3 D2 D1 D0
0 00000
MFRACx[17
]
MFRACx[16] MFRACx[15] MFRACx[14]
MFRACx[13
]
MFRACx[1
2]
MFRACx[11
]
MFRACx[
10]
1 00001 Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd
2 00010 MFRACx[9] MFRACx[8] MFRACx[7] MFRACx[6] MFRACx[5] MFRACx[4] MFRACx[3]
MFRACx[
2]
3 00011 Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd
4 00100 MFRACx[1] MFRACx[0] MINTx[7] MINTx[6] MINTx[5] MINTx[4] MINTx[3] MINTx[2]
5 00101 Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd
6 00110 MINTx[1] MINTx[0] Px[16] Px[15] Px[14] Px[13] Px[12] Px[11]
7 00111 Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd
8 01000 Px[10] Px[9] Px[8] Px[7] Px[6] Px[5] Px[4] Px[3]
9 01001 Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd
10 01010 Px[2] Px[1] Px[0] M1_x[16] M1_x[15] M1_x[14] M1_x[13] M1_x[12]
11 01011 Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd
12 01100 M1_x[11] M1_x[10] M1_x[9] M1_x[8] M1_x[7] M1_x[6] M1_x[5] M1_x[4]
13 01101 Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd
14 01110 M1_x[3] M1_x[2] M1_x[1] M1_x[0] Nx[10] Nx[9] Nx[8] Nx[7]
15 01111 Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd
16 10000 Nx[6] Nx[5] Nx[4] Nx[3] Nx[2] Nx[1] Nx[0] BWx[6]
17 10001 Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd
18 10010 BWx[5] BWx[4] BWx[3] BWx[2] BWx[1] BWx[0] Q1_TYPEx
Q0_TYPE
x
19 10011 Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd
20 10100
MODE_SEL
x[1]
MODE_SELx[
0]
01
OE1x OE0x Rsvd Rsvd
21 10101 CLK-SELx
AUTO_MANx
[1]
AUTO_MANx
[0]
HOLD_OFF
ADC_RATE
x[1]
ADC_RATE
x[0]
LCK_WINx[
1]
LCK_WIN
x[0]
22 10110 1 0 1 0
DBL_REFC
LKx
0
01
23 10111
CLK_ACTIV
Ex
HOLDOVERx CLK1BADx CLK0BADx REFBADx LOCKx Rsvd Rsvd
IDT8T49N366AASGI REVISION A JUNE 28, 2013 11 ©2013 Integrated Device Technology, Inc.
IDT8T49N366I Data Sheet FEMTOCLOCK
®
NG TRIPLE UNIVERSAL FREQUENCY TRANSLATOR
TM
Table 4E. Configuration-Specific Control Bits
Table 4F. Global Control Bits
Register Bits Function
Q0_TYPEx
Determines the output type for output pair Q0, nQ0 for PLLx
0 = LVPECL
1 = LVDS
Q1_TYPEx
Determines the output type for output pair Q1, nQ1 for PLLx.
0 = LVPECL
1 = LVDS
Px[16:0] Reference Pre-Divider for PLLx.
M1_x[16:0] Integer Feedback Divider in Lower Feedback Loop for PLLx.
M_INTx[7:0] Feedback Divider, Integer Value in Upper Feedback Loop for PLLx.
M_FRACx[17:0] Feedback Divider, Fractional Value in Upper Feedback Loop for PLLx.
Nx[10:0] Output Divider for PLLx.
BWx[6:0]
Internal Operation Settings for PLLx.
Please use IDT IDT8T49N366I Configuration Software to determine the correct settings for these bits for the
specific configuration. Alternatively, please consult with IDT directly for further information on the functions of these
bits.The function of these bits are explained in Tables 4J and 4K.
Register Bits Function
MODE_SELx[1:0]
PLL Mode Select for PLLx
00 = Low Bandwidth Frequency Translator
01 = Frequency Synthesizer
10 = High Bandwidth Frequency Translator
11 = High Bandwidth Frequency Translator
OE0x
Output Enable Control for Output 0 for PLLx.
0 = Output Q0, nQ0 disabled
1 = Output Q0, nQ0 enabled
OE1x
Output Enable Control for Output 1 for PLLx.
0 = Output Q1, nQ1 disabled
1 = Output Q1, nQ1 enabled
Rsvd Reserved bits - user should write a ‘0’ to these bit positions if a write to these registers is needed
AUTO_MANx[1:0]
Selects how input clock selection is performed for PLLx.
00 = Manual Selection via pin only
01= Automatic, non-revertive
10 = Automatic, revertive
11= Manual Selection via register only
CLK_SELx
In manual clock selection via register mode for PLLx, this bit will command which input clock is selected. In the
automatic modes, this indicates the primary clock input. In manual selection via pin mode, this bit has no effect.
0 = CLK0
1 = CLK1
ADC_RATEx[1:0]
Sets the ADC sampling rate in Low-Bandwidth Mode as a fraction of the REFCLK input frequency for PLLx
00 = REFCLK Frequency / 16 when doubler is disabled
01 = REFCLK Frequency / 8 when doubler is disabled
10 = REFCLK Frequency / 4 (recommended) when doubler is disabled
11 = REFCLK Frequency / 2 when doubler is disabled
LCK_WINx[1:0]
Sets the width of the window in which a new reference edge must fall relative to the feedback edge for PLLx:
00 = 2usec (recommended), 01 = 4usec, 10 = 8usec, 11 = 16usec
DBL_REFCLKx
When set, this bit will double the frequency of the REFCLK input before applying it to the Phase-Frequency
Detector for PLLx
IDT8T49N366AASGI REVISION A JUNE 28, 2013 12 ©2013 Integrated Device Technology, Inc.
IDT8T49N366I Data Sheet FEMTOCLOCK
®
NG TRIPLE UNIVERSAL FREQUENCY TRANSLATOR
TM
Table 4G. Global Status Bits
Table 4H. BW[6:0] Bits
Table 4I. Functions of Fields in BW[6:0]
Register Bits Function
CLK0BADx
Status Bit for input clock 0 for PLLx.
0 = input 0 good
1 = input 0 bad. Self clears when input clock returns to good status
CLK1BADx
Status Bit for input clock 1 for PLLx.
0 = input 0 good
1 = input 0 bad. Self clears when input clock returns to good status
REFBADx
Status Bit for PLLx.
0= REFCLK input good
1 = REFCLK input bad. Self-clears when the REFCLK clock returns to good status
LOCKx
Status bit for PLLx. This bit is mirrored on LOCKx pin.
0 = PLL unlocked
1 = PLL locked
HOLDOVERx
Status Bit for PLLx.
0 = Input to phase detector is within specifications and device is tracking to it
1 = Phase detector input not within specifications and DCXO is frozen at last value
CLK_ACTIVEx Status Bit for PLLx. Indicates which input clock is active. Automatically updates during fail-over switching.
Mode BWx[6] BWx[5] BWx[4] BWx[3] BWx[2] BWx[1] BWx[0]
Synthesizer Mode
PLL2_LF
x[1]
PLL2_LF
x[0]
DSM_ORDx DSM_ENx
PLL2_CP
x[1]
PLL2_CP
x[0]
PLL2_LOW
_ICPx
High-Bandwidth Mode
PLL2_LF
x[1]
PLL2_LF
x[0]
DSM_ORDx DSM_ENx
PLL2_CP
x[1]
PLL2_CP
x[0]
PLL2_LOW
_ICPx
Low-Bandwidth Mode
ADC_GAIN
x[3]
ADC_GAIN
x[2]
ADC_GAIN
x[1]
ADC_GAIN
x[0]
PLL1_CP
x[1]
PLL1_CP
x[0]
PLL2_LOW
_ICPx
Register Bits Function
PLL2_LFx[1:0]
Sets loop filter values for upper loop PLL in Frequency Synthesizer & High-Bandwidth modes for PLLx.
Defaults to setting of 00 when in Low Bandwidth Mode. See Table 4L for settings.
DSM_ORDx Sets Delta-Sigma Modulation to 2nd (0) or 3rd order (1) operation for PLLx.
DSM_ENx
Enables Delta-Sigma Modulator for PLLx:
0 = Disabled - feedback in integer mode only
1 = Enabled - feedback in fractional mode
PLL2_CPx[1:0]
Upper loop PLL charge pump current settings for PLLx:
00 = 173A (defaults to this setting in Low Bandwidth Mode)
01 = 346A
10 = 692A
11 = reserved
PLL2_LOW_ICPx
Reduces Charge Pump current by 1/3 to reduce bandwidth variations resulting from higher feedback register
settings or high VCO operating frequency (>2.4GHz) for PLLx.
ADC_GAINx[3:0] Gain setting for ADC in Low Bandwidth Mode.
PLL1_CPx[1:0]
Lower loop PLL charge pump current settings (lower loop is only used in Low Bandwidth Mode) for PLLx:
00 = 800A
01 = 400A
10 = 200
A
11 = 100A
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36

8T49N366A-999ASGI8

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