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8T49N366A-999ASGI8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
IDT8T49N366AASGI REVISION A JUNE 28, 2013 22 ©2013 Integrated Device Technology, Inc.
IDT8T49N366I Data Sheet FEMTOCLOCK
®
NG TRIPLE UNIVERSAL FREQUENCY TRANSLATOR
TM
Wiring the Differential Input to Accept Single-Ended Levels
Figure 4 shows how a differential input can be wired to accept single
ended levels. The reference voltage V
1
= V
CC
/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V
1
in the center of the input voltage swing. For
example, if the input clock swing is 2.5V and V
CC
= 3.3V, R1 and R2
value should be adjusted to set V
1
at 1.25V. The values below are for
when both the single ended swing and V
CC
are at the same voltage.
This configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the input will
attenuate the signal in half. This can be done in one of two ways.
First, R3 and R4 in parallel should equal the transmission line
impedance. For most 50 applications, R3 and R4 can be 100. The
values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however V
IL
cannot be less
than -0.3V and V
IH
cannot be more than V
CC
+ 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 4. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
Receiv er
+
-R4
100
R3
100
RS Zo = 50 Ohm
Ro
Driver
VCC
VCC
R2
1K
R1
1K
C1
0.1uF
Ro + Rs = Zo
V1
VC C VC C
IDT8T49N366AASGI REVISION A JUNE 28, 2013 23 ©2013 Integrated Device Technology, Inc.
IDT8T49N366I Data Sheet FEMTOCLOCK
®
NG TRIPLE UNIVERSAL FREQUENCY TRANSLATOR
TM
Differential Clock Input Interface
The CLKx / nCLKx accepts LVDS, LVPECL, LVHSTL, HCSL and
other differential signals. Both V
SWING
and V
OH
must meet the V
PP
and V
CMR
input requirements. Figures 5A to 5E show interface
examples for the CLKx / nCLKx input driven by the most common
driver types. The input interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 5A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
Figure 5A. CLKx/ nCLKx Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 5C. CLKx/ nCLKx Input
Driven by a 2.5V LVPECL Driver
Figure 5E. CLKx/ nCLKx Input
Driven by a 2.5V HCSL Driver
Figure 5B. CLKx/ nCLKx Input
Driven by a 2.5V LVPECL Driver
Figure 5D. CLKx/ nCLKx Input
Driven by a 2.5V LVDS Driver
R1
50
R2
50
1.
8V
Zo
=
50
Zo
=
50
C
L
K
nC
L
K
2
.
5V
L
VH
S
T
L
I
DT
O
pen Emitte
r
L
VH
S
TL Driv
er
Differential
I
nput
R3
250
R4
250
R1
6
2.
5
R2
6
2.
5
2
.
5V
Zo
=
50
Zo
=
50
C
L
K
nC
L
K
2
.
5V
2
.
5V
L
VPE
CL
Differential
I
nput
HCSL
*
R
3
33
*R4
33
C
L
K
nC
L
K
2
.
5V
2
.
5V
Zo
=
50
Zo
=
50
D
i
ffe
r
e
nti
a
l
I
nput
R1
50
R2
50
*O
ptional
–
R
3
a
n
d
R4
ca
n
be
0
C
L
K
nC
L
K
D
i
ffe
r
e
nti
a
l
I
nput
L
VPE
CL
2
.
5V
Zo
=
50
Zo
=
50
2
.
5V
R1
50
R2
50
R3
1
8
2
.
5V
R1
1
00
L
VD
S
C
L
K
nC
L
K
2
.
5V
Differential
I
nput
Zo
=
50
Zo
=
50
IDT8T49N366AASGI REVISION A JUNE 28, 2013 24 ©2013 Integrated Device Technology, Inc.
IDT8T49N366I Data Sheet FEMTOCLOCK
®
NG TRIPLE UNIVERSAL FREQUENCY TRANSLATOR
TM
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (Z
T
) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z
0
) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
standard termination schematic as shown in Figure 6A can be used
with either type of output structure. Figure 6B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
LVDS Termination
LVDS
Driver
LVDS
Driver
LVD S
Receiver
LVD S
Receiver
Z
T
C
Z
O
Z
T
Z
O
Z
T
Z
T
2
Z
T
2
Figure 6A. Standard Termination
Figure 6B. Optional Termination
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8T49N366A-999ASGI8

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IDT
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Clock Generators & Support Products Femto NG Clock Generator
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