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XR22804IL56-F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47
© 2015 Exar Corporation
XR22804
13 / 47 exar.com/XR22804
Rev 1B
ICMP checksum offload over IPV4 and IPV6 as well as header checksum offload in IPV4. On chip RAM provides all
required packet buffering.
In Windows OS, using the Exar custom Ethernet driver, the properties dialog, advanced properties can be used to set the
pause frame flow control, speed and duplex, auto-negotiation, checksum offload, and Ethernet remote wakeup settings. By
default, the Ethernet MAC will honor incoming pause frames sent by a peer Ethernet device, but will not generate pause
frames. Auto-MDIX is always enabled.
Ethernet Remote Wakeup
If the XR22804 hub is configured as a self-powered device and has Ethernet remote wakeup enabled, the XR22804 will
request the USB host to resume in response to a magic packet or a link state change on the Ethernet port. When the USB
host is suspended, the Ethernet Phy remains active and the XR22804 is able to both meet USB suspend mode power
requirements as well as respond to magic packet and link state changes.
The magic packet is an Ethernet packet with specific content, i.e. 6 bytes of 0xFF, followed by 16 repetitions of the target
MAC address (MAC address of the XR22804 device). This content can occur anywhere in the incoming packet payload.
The link state change will wake the USB host if the link is down when the USB host is suspended and then the link goes up,
or if the link is up when the USB host is suspended and then the link goes down.
UART
The UART can be configured via USB control transfers from the USB host. The UART transmitter and receiver sections are
described separately in the following sections. At power-up, the XR22804 will default to 9600 bps, 8 data bits, no parity bit,
1 stop bit, and no flow control. If a standard CDC-ACM driver accesses the XR22804, defaults will change. See Remote
Wakeup section on page 11.
UART transmitter
The transmitter consists of a 1024-byte TX FIFO and a Transmit Shift Register (TSR). Once a bulk-out packet has been
received and the CRC has been validated, the data bytes in that packet are written into the TX FIFO of the specified UART
channel. Data from the TX FIFO is transferred to the TSR when the TSR is idle or has completed sending the previous data
byte. The transmitter sends the start bit followed by the data bits (starting with the LSB), inserts the proper parity-bit if
enabled, and adds the stop-bit(s). The transmitter can be configured for 7 or 8 data bits with or without parity or 9 data bits
without parity. If 9 bit data is selected without wide mode, the 9th bit will always be ’0’.
UART transmitter - Wide mode
When both 9 bit data and wide mode are enabled, two bytes of data must be written. The first byte that is loaded into the TX
FIFO are the first 8 bits (data bits 7-0) of the 9-bit data. Bit-0 of the second byte that is loaded into the TX FIFO is bit-8 of the
9-bit data. The data that is transmitted on the TX pin is as follows: start bit, 9-bit data, stop bit. Use the TX_WIDE_MODE
register to enable transmit wide mode.
UART receiver
The receiver consists of a 1024-byte RX FIFO and a Receive Shift Register (RSR). Data that is received in the RSR via the
RX pin is transferred into the RX FIFO. Data from the RX FIFO is sent to the USB host in response to a bulk-in request.
Depending on the mode, error / status information for that data character may or may not be stored in the RX FIFO with the
data.
UART receiver - Normal mode with 7 or 8-bit data
Data that is received is stored in the RX FIFO. Any parity, framing or overrun error or break status information related to the
data is discarded. Receive data format is shown in Figure 1.
© 2015 Exar Corporation
XR22804
14 / 47 exar.com/XR22804
Rev 1B
UART receiver - Normal mode with 9-bit data
The first 8 bits of data received is stored in the RX FIFO. The 9th bit as well as any parity, framing or overrun error or break
status information related to the data is discarded.
Figure 1: UART Normal Receive Data Format with 7 or 8-bit data
UART receiver - Wide mode with 7 or 8-bit data
Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the received data. The sec-
ond byte consists of the error bits and break status. Wide mode receive data format is shown in Figure 2. Use the
RX_WIDE_MODE register to enable receive wide mode. Use the RX_WIDE_MODE register to enable receive wide mode.
UART receiver - Wide mode with 9-bit data
Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the first 8 bits of the received
data. The 9th bit received is stored in the bit 0 of the second byte. The parity bit is not received / checked. The remainder of
the 2nd byte consists of the framing and overrun error bits and break status.
Figure 2: UART Receive Wide Mode Data Format with 7, 8 or 9-bit data
Error flags are also available from the ERROR_STATUS register and the interrupt packet, however these flags are historical
flags indicating that an error has occurred since the previous request. Therefore, no conclusion can be drawn as to which
specific byte(s) may have contained an actual error in this manner.
RX FIFO Low Latency
In normal operation all bulk-in transfers will be of maxPacketSize bytes (512 bytes in hi-speed mode and 64 bytes in full-
speed mode) to improve throughput and to minimize host processing. When there are 512 / 64 bytes of data in the RX FIFO,
the XR22804 will acknowledge a bulk-in request from the host and transfer the data packet. If there is less than 512 bytes in
1
ST
byte
7, 8 or 9-bit data
7 6 5 4 3 2 1 0
7 = ‘0’ in 7 bit mode
1st byte
2nd byte
9 bit mode
7 6 5 4 3 2 1 0
x x x x O F B P
1st byte
B = Break
F = Framing Error
O = Overrun Error
2nd byte
7 or 8 bit mode
P = Parity Error (= ‘0’ if not enabled)
7 = ‘0’ in 7 bit mode
x = ‘0’
7 6 5 4 3 2 1 0
x x x x O F B 8B = Break
F = Framing Error
O = Overrun Error
x = ‘0’
© 2015 Exar Corporation
XR22804
15 / 47 exar.com/XR22804
Rev 1B
the RX FIFO, the XR22804 may NAK the bulk-in request indicating that data is not ready to transfer at that time. However, if
there is less than 512 bytes in the RX FIFO and no data has been received for more than 3 character times, the XR22804
will acknowledge the bulk-in request and transfer any data in the RX FIFO to the USB host.
In some cases, especially when the baud rate is low, this increases latency unacceptably. The XR22804 has a low latency
register bit that will cause the XR22804 to immediately transfer any received data in the RX FIFO to the USB host, i.e. it will
not wait for 3 character times. The custom driver may automatically set the RX_CONTROL register to force the XR22804 to
be in the low latency mode, or the user may manually set this bit. With the CDC-ACM driver, the low latency mode is auto-
matically set whenever the baud rate is set to a value of less than 46921 bps using the CDC_ACM_IF_SET_LINE_COD-
ING command.
GPIO
There can be up to 8 GPIO pins in the XR22804 UART including the UART RX and TX pins. These GPIO pins may be con-
figured as UART GPIO, or for other UART functions, e.g. RTS# function, or be assigned to the EDGE. Refer to Enhanced
Dedicated GPIO Entity section on page 17.
Automatic RTS / CTS hardware flow control
E[n]/RTS#/RS485/G[n] and E[n]/CTS#/G[n] of each UART channel may be enabled as the RTS# and CTS# signals for Auto
RTS/CTS flow control when GPIO_MODE[2:0] = ’001’ and FLOW_CONTROL[2:0] = ’001’. Automatic RTS flow control is
used to prevent data overrun errors in local RX FIFO by de-asserting the RTS signal to the remote UART. When there is
room in the RX FIFO, the RTS pin will be re-asserted. Automatic CTS flow control is used to prevent data overrun to the
remote RX FIFO. The CTS# input is monitored to suspend / restart the local transmitter (see Figure 3):
Figure 3: Auto RTS / CTS Hardware Flow Control
Transm itter
Auto C TS
Monitor
Receiver FIFO
Trigger Reached
Auto R TS
Trigger Level
Remote UART
UARTB
RTSA#
CTSB#
TXB
RXA
ON ON
OFF
ON ON
OFF
1
2
3
4
1) COM port opened, RX FIFO empty, RTSA# output is asserted
2) Signal propagated to CTSB# input
3) Data bytes enter TX FIFO, begin transmitting on TXB
4) Data propagates to Receiving device RXA
5) RX FIFO reaches threshold
6) RTSA# de-asserts
7) Signal propagates to CTSB# input
8) Transmission stops on TXB
9) USB Bulk-In empties RX FIFO below threshold, RTSA# is asserted
10) Signal propagated to CTSB# input
11) Data bytes resume transmitting on TXB
5
6
7
8
9
10
11
RTSA# CTSB#
TXBRXA
CTSA#
TXA
RTSB#
RXB
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Transmitter
Auto CTS
Monitor
Local UART
UARTA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47

XR22804IL56-F

Mfr. #:
Buy XR22804IL56-F
Manufacturer:
MaxLinear
Description:
I/O Controller Interface IC Hi-Speed USB 10/100 Eth Brdg w 4CH UART
Lifecycle:
New from this manufacturer.
Delivery:
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