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XR22804IL56-F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47
© 2015 Exar Corporation
XR22804
37 / 47 exar.com/XR22804
Rev 1B
0x3D6
EDGE_INTR_POS_
EDGE_1 [31:24]
E31 E30 E29 E28 E27 E26 E25 E24
EDGE_INTR_POS_
EDGE_1 [23:16]
E23 E22 E21 E20 E19 E18 E17 E16
0x3D7
EDGE_INTR_NEG_
EDGE_1 [31:24]
E31 E30 E29 E28 E27 E26 E25 E24
EDGE_INTR_NEG_
EDGE_1 [23:16]
E23 E22 E21 E20 E19 E18 E17 E16
0x3D8
EDGE_PWM0_CTRL MSB
[15:8]
0000000CMD[2]
EDGE_PWM0_CTRL LSB
[7:0]
CMD[1:0] EN PIN[4:0]
0x3D9
EDGE_PWM0_HIGH MSB
[15:8]
0000 VALUE[11:8]
EDGE_PWM0_HIGH LSB
[7:0]
VALUE [7:0]
0x3DA
EDGE_PWM0_LOW MSB
[15:8]
0000 VALUE[11:8]
EDGE_PWM0_LOW LSB
[7:0]
VALUE [7:0]
0x3DB
EDGE_PWM1_CTRL MSB
[15:8]
0000000CMD[2]
EDGE_PWM1_CTRL
LSB [7:0]
CMD[1:0] EN PIN[4:0]
0x3DC
EDGE_PWM1_HIGH MSB
[15:8]
0000 VALUE[11:8]
EDGE_PWM1_HIGH LSB
[7:0]
VALUE [7:0]
0x3DD
EDGE_PWM1_LOW MSB
[15:8]
0000 VALUE[11:8]
EDGE_PWM1_LOW LSB
[7:0]
VALUE [7:0]
Table 9: XR22804 HID Register Map
Address Register Name
Bit 7
(15)
Bit 6
(14)
Bit 5
(13)
Bit 4
(12)
Bit 3
(11)
Bit 2
(10)
Bit 1
(9)
Bit 0
(8)
© 2015 Exar Corporation
XR22804
38 / 47 exar.com/XR22804
Rev 1B
HID Register Descriptions
Note that all register reset default values are ’0’ unless otherwise specified. All registers are 16 bits.
I
2
C_SCL_LOW (0x341) - Read/Write
I
2
C_SCL_HIGH (0x342) - Read/Write
EDGE_FUNC_SEL_0 (0x3C0) - Read/Write
EDGE_DIR_0 (0x3C1) - Read/Write
Note that when setting direction of an EDGE IO to output, the EDGE_PULL_UP for that IO pin should also be disabled and
when setting an EDGE IO pin to input, the EDGE_PULL_UP for that IO pin should also be enabled.
Bit Default Description
15:0 0x0144
Value
Specifies the number of periods that SCL will be asserted low by the XR22804 I
2
C master. Note that in clock
stretching, the I
2
C slave may extend the SCL low period to delay the next transaction. For 100 kbps transfer
rate this value must be at least 252 (0x00FC) and the sum of high and low periods must be at least 600
(0x0258). For 400kbps transfer rate this value must be at least 78 (0x004E) and the sum of the high and low
periods must be at least 150 (0x0096). Measured in 60 MHz core clock periods, i.e. approximately 16.7 ns.
Bit Default Description
15:0 0x0114
Value
Specifies the number of periods that SCL will be asserted high by the XR22804 I
2
C master. Note that another
multi-master may assert SCL low before the XR22804 high period is completed. For 100 kbps transfer rate this
value must be at least 240 (0x00F0) and the sum of the high and low periods must be at least 600 (0x0258).
For 400 kbps transfer rate this value must be at least 36 (0x0024) and the sum of the high and low periods must
be at least 150 (0x0096). Measured in 60 MHz core clock periods, i.e. approximately 16.7 ns
Bit Default Description
15:0 0x0000
E[15:0]
0: IO is assigned to the UART / GPIO function. IO pin controlled using UART registers.
1: IO is assigned to the EDGE function. IO pin controlled using EDGE registers.
Bit Default Description
15:0 0x0000
E[15:0]
0: IO pin assigned to EDGE function is configured as an input
1: IO pin assigned to EDGE function is configured as an output.
© 2015 Exar Corporation
XR22804
39 / 47 exar.com/XR22804
Rev 1B
EDGE_SET_0 (0x3C2) - Write Only
EDGE_CLEAR_0 (0x3C3) - Write Only
EDGE_STATE_0 (0x3C4) - Read/Write
EDGE_TRI_STATE_0 (0x3C5) - Read/Write
EDGE_OPEN_DRAIN_0 (0x3C6) - Read/Write
Bit Default Description
15:0 0x0000
E[15:0]
0: No effect
1: Set IO pin assigned to EDGE function and configured as an output to a logic ‘1’
Bit Default Description
15:0 0x0000
E[15:0]
0: No effect
1: Clear IO pin assigned to EDGE function and configured as an output to a logic ‘0’
Bit Default Description
15:0 0x0000
E[15:0]
Writing in this register sets or clears the EDGE IO pin(s) configured as an output. Writing to an EDGE pin con-
figured as an input has no effect. Reading this register returns the state of each IO pin configured as an EDGE
pin irrespective of whether it is configured as an input or output. Note that output transitions across multiple IO
pins may be slightly staggered. Refer to EDGE section on page 17.
0: Write clears the corresponding bit to a ‘0’. Read returns the current state.
1: Write sets the corresponding bit to a ‘1’. Read returns the current state.
Bit Default Description
15:0 0x0000
E[15:0]
0: IO pin assigned to EDGE function and configured as an output is actively driven
1: IO pin assigned to EDGE function and configured as an output is tri-stated
Bit Default Description
15:0 0x0000
E[15:0]
Note that XR22804 open drain outputs have a weak internal pull-up.
0: IO pin assigned to EDGE function and configured as an output is a push-pull output
1: IO pin assigned to EDGE function and configured as an output is an open drain output
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47

XR22804IL56-F

Mfr. #:
Buy XR22804IL56-F
Manufacturer:
MaxLinear
Description:
I/O Controller Interface IC Hi-Speed USB 10/100 Eth Brdg w 4CH UART
Lifecycle:
New from this manufacturer.
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