LTC2636
15
2636fc
For more information www.linear.com/LTC2636
PIN FUNCTIONS
V
CC
(Pin 1/1): Supply Voltage Input. 2.7V ≤ V
CC
≤ 5.5V
(LTC2636-L) or 4.5V ≤ V
CC
≤ 5.5V (LTC2636-H). Bypass
to GND with a 0.1μF capacitor.
V
OUT
A to V
OUT
H (Pins 2-5, 10-13/2-5, 12-15): DAC
Analog Voltage Outputs.
CS/LD (Pin 6/7): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on
SDI into the register. When CS/LD is taken high, SCK
is disabled and the specified command (see Table 1) is
executed.
SCK (Pin 7/8): Serial Interface Clock Input. CMOS and
TTL compatible.
SDI (Pin 8/9): Serial Interface Data Input. Data on SDI
is clocked into the DAC on the rising edge of SCK. The
LTC2636 accepts input word lengths of either 24 or 32 bits.
REF (Pin 9/11): Reference Voltage Input or Output. When
External Reference mode is selected, REF is an input
(1V ≤ V
REF
≤ V
CC
) where the voltage supplied sets the
full-scale DAC output voltage. When Internal Reference
is selected, the 10ppm/°C 1.25V (LTC2636-L) or 2.048V
(LTC2636-H) internal reference (half full-scale) is avail
-
able at REF. This output may be bypassed to GND with up
to 10μF, and must be buffered when driving external DC
load current.
GND (Pin 14/16): Ground.
LDAC (Pin 6, MSOP only): Asynchronous DAC Update
Pin. If CS/LD is high, a falling edge on LDAC immediately
updates the DAC registers with the contents of the input
registers (similar to a software update). If CS/LD is low
when LDAC goes low, the DAC registers are updated after
CS/LD returns high. A low on the LDAC pin powers up
the DACs. A software power down command is ignored if
LDAC is low. If the LDAC functionality is not being used,
the LDAC pin should be tied high.
CLR (Pin 10, MSOP only): Asynchronous Clear Input.
A logic low at this level-triggered input clears all regis-
ters and causes the DAC voltage output to reset to Zero
(LTC2636-Z) or Mid-scale (LTC2636-MI/-MX). CMOS and
TTL compatible.
Exposed Pad (Pin 15, DFN Only): Ground. Must be sol-
dered to PCB Ground.
(DFN/MSOP)
