LTC2636
19
2636fc
For more information www.linear.com/LTC2636
OPERATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
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20
21
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24
C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X XC3
CS/LD
SCK
SDI
COMMAND WORD ADDRESS DATA WORD
24-BIT INPUT WORD
2636 F03a
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
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24 25 26 27 28 29 30 31 32
C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X XX X X X X X X X 3C
CS/LD
SCK
SDI
COMMAND WORD DATA WORD
8 DON’T-CARE BITS ADDRESS
2636 F03b
32-BIT INPUT WORD
Figure 3a. LTC2636-12 24-Bit Load Sequence (Minimum Input Word).
LTC2636-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Care Bits;
LTC2636-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Care Bits
Figure 3b. LTC2636-12 32-Bit Load Sequence.
LTC2636-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Care Bits;
LTC2636-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Care Bits
LTC2636
20
2636fc
For more information www.linear.com/LTC2636
OPERATION
at the REF pin. Adding bypass capacitance to the REF pin
will improve noise performance; and up to 10μF can be
driven without oscillation. The REF output must be buff
-
ered when driving an external DC load current.
Alternatively, the DAC can operate in External Reference
mode using command 0111b. In this mode, an input
voltage supplied externally to the REF pin provides the
reference (1V V
REF
V
CC
) and the supply current is
reduced. The external reference voltage supplied sets the
full-scale DAC output voltage. External Reference mode is
the power-on default for LTC2636-HMX/-LMX.
The reference mode of LTC2636-HZ/-LZ/-HMI/-LMI (Internal
Reference power-on default), can be changed by software
command after power-up. The same is true for LTC2636-
HMX/-LMX (External Reference power-on default).
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever less
than eight DAC outputs are needed. When in power-
down, the buffer amplifiers, bias circuits, and integrated
reference circuits are disabled, and draw essentially zero
current. The DAC outputs are put into a high-impedance
state, and the output pins are passively pulled to ground
through individual 200k resistors. Input- and DAC-register
contents are not disturbed during power-down.
Any DAC channel or combination of channels can be put
into power-down mode by using command 0100b in com-
bination with the appropriate DAC address, (n). The sup-
ply current is reduced approximately 10% for each DAC
powered down. The integrated reference is automatically
powered down when external reference is selected using
command 0111b. In addition, all the DAC channels and
the integrated reference together can be put into power
-
down mode using Power Down Chip command
0101b.
When the integrated reference and all DAC channels are
in power
-down mode, the REF pin becomes high imped
-
ance (typically > 1GΩ). For all power-down commands
the 16- bit data word is ignored.
Normal operation resumes after executing any command
that includes a DAC update, (as shown in Table 1) or using
the asynchronous LDAC pin. The selected DAC is powered
up as its voltage output is updated. When a DAC which
is in a powered-down state is powered up and updated,
normal settling is delayed. If less than eight DACs are in
a powered-down state prior to the update command, the
power-up delay time is 10μs. However, if all eight DACs
and the integrated reference are powered down, then the
main bias generation circuit block has been automatically
shut down in addition to the DAC amplifiers and refer-
ence buffers. In this case, the power up delay time is
12μs. The power-up of the integrated reference depends
on the command that powered it down. If the reference
is powered down using the Select External Reference
Command (0111b), then it can only be powered back
up using Select Internal Reference Command (0110b).
However, if the reference was powered down using Power
Down Chip Command (0101b), then in addition to Select
Internal Reference Command (0110b), any command (in
software or using the LDAC pin) that powers up the DACs
will also power up the integrated reference.
Voltage Outputs
The LTC2636s integrated rail-to-rail amplifiers have guar-
anteed load regulation when sourcing or sinking up to
10mA at 5V, and 5mA at 3V.
Load regulation is a measure of the amplifiers ability to
maintain the rated voltage accuracy over a wide range of
load current. The measured change in output voltage per
change in forced load current is expressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to ohms. The amplifiers DC output
impedance is 0.1Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 50Ω typical channel resistance of the output devices
(e.g., when sinking 1mA, the minimum output voltage
is 50Ω 1mA, or 50mV). See the graph Headroom at
Rails vs. Output Current in the Typical Performance
Characteristics section.
The amplifier is stable driving capacitive loads of up to
500pF.
LTC2636
21
2636fc
For more information www.linear.com/LTC2636
OPERATION
2636 F04
INPUT CODE
(b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
0V
2,0480 4,095
INPUT CODE
OUTPUT
VOLTAGE
(a)
V
REF
= V
CC
V
REF
= V
CC
(c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
Figure 4. Effects of Rail-to-Rail Operation On a DAC Transfer Curve (Shown for 12 Bits).
(a) Overall Transfer Function
(b) Effect of Negative Offset for Codes Near Zero
(c) Effect of Positive Full-Scale Error for Codes Near Full-Scale
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is lim-
ited to voltages within the supply range.
Since the analog output of the DAC cannot go below
ground, it may limit for the lowest codes as shown in
Figure 4b. Similarly, limiting can occur near full-scale
when the REF pin is tied to V
CC
. If V
REF
= V
CC
and the
DAC full-scale error (FSE) is positive, the output for the
highest codes limits at V
CC
, as shown in Figure 4c. No
full-scale limiting can occur if V
REF
is less than V
CC
–FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
Board Layout
The PC board should have separate areas for the analog
and digital sections of the circuit. A single, solid ground
plane should be used, with analog and digital signals care-
fully routed over separate areas of the plane. This keeps
digital signals away from sensitive analog signals and
minimizes the interaction between digital ground currents
and the analog section of the ground plane. The resistance
from the LTC2636 GND pin to the ground plane should
be as low as possible. Resistance here will add directly to
the effective DC output impedance of the device (typically
0.1Ω). Note that the LTC2636 is no more susceptible to
this effect than any other parts of this type; on the con-
trary, it allows layout-based performance improvements
to shine rather than limiting attainable per
formance with
excessive internal resistance.
Another technique for minimizing errors is to use a sepa
-
rate power ground return trace on another board layer.
The trace should run between the point where the power
supply is connected to the board and the DAC ground pin.
Thus the DAC ground pin becomes the common point for
analog ground, digital ground, and power ground. When
the LTC2636 is sinking large currents, this current flows
out the ground pin and directly to the power ground trace
without affecting the analog ground plane voltage.
It is sometimes necessary to interrupt the ground plane
to confine digital ground currents to the digital portion of
the plane. When doing this, make the gap in the plane only
as long as it needs to be to serve its purpose and ensure
that no traces cross over the gap.

LTC2636IMS-HZ10#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 10-Bit SPI Octal DAC (4.096V ref, Reset to Zero-Scale)
Lifecycle:
New from this manufacturer.
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