DS21Q354N Datasheet DS21Q352N, DS21Q352, DS21Q552N+ | P10-P12

DALLAS SEMICONDUCTOR DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet

December 29, 1998 10

C17 TSER2 I Transmit Serial Data for SCT2.

C10 TSER3 I Transmit Serial Data for SCT3.

K20 TSER4 I Transmit Serial Data for SCT4.

W10 TSIG1 I Transmit Signaling Input for SCT1.

C18 TSIG2 I Transmit Signaling Input for SCT2.

A10 TSIG3 I Transmit Signaling Input for SCT3.

L19 TSIG4 I Transmit Signaling Input for SCT4.

W12 TSSYNC1 I Transmit System Sync for SCT1.

B18 TSSYNC2 I Transmit System Sync for SCT2.

D10 TSSYNC3 I Transmit System Sync for SCT3.

K19 TSSYNC4 I Transmit System Sync for SCT4.

V1 TSYNC1 I/O Transmit Sync for SCT1.

D20 TSYNC2 I/O Transmit Sync for SCT2.

C7 TSYNC3 I/O Transmit Sync for SCT3.

R18 TSYNC4 I/O Transmit Sync for SCT4.

W11 TSYSCLK1 I Transmit System Clock for SCT1.

A19 TSYSCLK2 I Transmit System Clock for SCT2.

A11 TSYSCLK3 I Transmit System Clock for SCT3.

N18 TSYSCLK4 I Transmit System Clock for SCT4.

Y1 TTIP1 O Transmit Analog Tip Output for SCT1.

Y3 TTIP2 O Transmit Analog Tip Output for SCT2.

Y5 TTIP3 O Transmit Analog Tip Output for SCT3.

Y7 TTIP4 O Transmit Analog Tip Output for SCT4.

W2 TVDD1 – Transmit Analog Positive Supply.

G19 TVDD2 – Transmit Analog Positive Supply.

D11 TVDD3 – Transmit Analog Positive Supply.

U19 TVDD4 – Transmit Analog Positive Supply.

W4 TVSS1 – Transmit Analog Signal Ground.

G18 TVSS2 – Transmit Analog Signal Ground.

C5 TVSS3 – Transmit Analog Signal Ground.

U18 TVSS4 – Transmit Analog Signal Ground.

K3 WR* (R/W*) I Write Input (Read/Write).

DALLAS SEMICONDUCTOR DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet

December 29, 1998 11

DS21Q352 / DS21Q552 / DS21Q354 / DS21Q554 PCB Land Pattern Figure 2

The diagram shown below is the lead pattern that will be placed on the target PCB. This is the same

pattern that would be seen as viewed through the MCM from the top.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A

rneg

i

3

rf

sync

3

rlink

3

rclk

i

3

dvss

3

co

3

tclko

3

tpos

i

3

dvdd

3

tsig

3

tsys

clk

3

rlclk

3

rlink

2

cs

2*

rclki

2

rpos

o

2

dvss

2

tch

clk

2

tsys

clk

2

dvss

2

B

rpos

o

3

rposi

3

dvdd

3

rclk

o

3

cs

3*

dvdd

3

dvss

3

tch

clk

3

dvss

3

tclk

3

dvss

2

dvdd

2

rclk

2

rpos

i

2

rneg

o

2

rsig

2

co

2

ts

sync

2

tclk

2

tneg

o

2

C

rsig

3

rneg

o

3

dvss

3

dvdd

3

tvss

3

tlink

3

tsync

3

tclk

i

3

tpos

o

3

tser

3

tch

blk

3

dvdd

2

dvss

2

rclk

o

2

rsigf

2

dvdd

2

tser

2

tsig

2

tpos

o

2

tpos

i

2

D

rsync

3

rsigf

3

rlclk

3

rvss

3

rvss

3

tlclk

3

ci

3

tneg

i

3

tneg

o

3

ts

sync

3

tvdd

3

rsync

2

rneg

i

2

rch

clk

2

rser

2

rm

sync

2

rf

sync

2

dvdd

2

tclk

i

2

tsync

2

E

rlos

3

rser

3

rclk

3

rvdd

3

rlos

2

tclk

o

2

tlink

2

tlclk

2

F

rlclk

1

rm

sync

3

rch

clk

3

8m

clk

3

rsys

clk

2

ci

2

tneg

i

2

tch

blk

2

G

rsync

1

rlink

1

rsys

clk

3

rch

blk

3

rch

blk

2

tvss

2

tvdd

2

dvdd

4

H

rsys

clk

1

rlos

1

dvss

1

A5 8m

clk

2

jtdo

2

rvss

2

dvss

4

J

rch

clk

1

rser

1

dvdd

1

dvss

1

rvdd

2

rvss

2

D1/

AD1

co

4

K

rsigf

1

liuc wr* rf

sync

1

cs

4*

rlclk

4

ts

sync

4

tser

4

L

rm

sync

1

rsig

1

rneg

o

1

rpos

o

1

A1 tch

clk

4

tsig

4

dvss

4

M

8m

clk

1

rch

blk

1

rclk

o

1

rclk

i

1

dvdd

4

rclk

4

tclk

4

dvdd

4

N

jtdi rd* rclk

1

dvdd

1

dvss

4

tsys

clk

4

tpos

o

4

tneg

o

4

P

rvdd

1

bts cs

1*

A7/

ALE

rneg

i

4

dvdd

4

tclk

o

4

tclk

i

4

R

tneg

i

1

rvss

1

rneg

i

1

rpos

i

1

rclk

i

4

tsync

4

tpos

i

4

tneg

i

4

T

mclk

1

rvss

1

tneg

o

1

A3 rclk

o

4

tlclk

4

tlink

4

ci

4

U

int* dvdd

1

A0 D7/

AD7

D5/

AD5

dvss

1

D3/

AD3

A6 D4/

AD4

mux D0/

AD0

rlink

4

dvss

4

rch

clk

4

rpos

o

4

test rneg

o

4

tvss

4

tvdd

4

tch

blk

4

V

tsync

1

A2 tlclk

1

D6/

AD6

dvdd

1

tclk

i

1

tpos

o

1

A4 co

1

tch

clk

1

rlos

4

rsync

4

8m

clk

4

rf

sync

4

rpos

i

4

rsigf

4

jtdo3 jtrst* jtdo4 rvss

4

W

tch

blk

1

tvdd

1

tpos

i

1

tvss

1

tlink

1

ci

1

tclk

o

1

dvss

1

tser

1

tsig

1

tsys

clk

1

ts

sync

1

jtms rsys

clk

4

D2/

AD2

rm

sync

4

rser

4

rvdd

4

rvss

4

mclk

2

Y

ttip

1

tring

1

ttip

2

tring

2

ttip

3

tring

3

ttip

4

tring

4

tclk

1

rtip

1

rring

1

rch

blk

4

rtip

2

rring

2

jtclk rtip

3

rring

3

rsig

4

rtip

4

rring

4

DALLAS SEMICONDUCTOR DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet

December 29, 1998 12

POWER SUPPLY DE-COUPLING

In a typical PCB layout for the DS21x5y, all of the VDD pins will connect to a common power plane and all

the VSS lines will connect to a common ground plane. There are three recommended methods for de-

coupling shown below in both schematic and pictorial form. As shown in the pictorials, the capacitors

should be symmetrically located about the device. The first shown in figure 3 uses standard capacitors,

two 33uf tantalums, two .33uf ceramics and two .01uf ceramics. The second method shown in figure 4

uses a single 68uf tantalum, two .33uf ceramics and two .01uf ceramics. The third method shown in figure

5 uses only four capacitors, two 1.5uf MLC and two .01uf ceramics. The 1.5uf is an MLC (Multi Layer

Ceramic) type. The MLC construction is a low inductance type, which allows a smaller value of

capacitance to be used. Since VDD and VSS signals will typically pass vertically to the power and ground

planes of a PCB, the de-coupling caps must be placed as close to the DS21Qx5y as possible and routed

vertically to power and ground planes.

De-coupling scheme using standard tantalum caps. Figure 3

De-coupling scheme using single 68uf cap. Figure 4

De-coupling scheme using MCL caps. Figure 5

All capacitor values in figures 3, 4 and 5 are in uf.

33 .33 .01 33 .33 .01

VDD VDD

DS21Qx5y

.01 .01

.33

33

DS21Qx5y

.01

VDD VDD

DS21Qx5y

1.5 1.5 .01

.01

1.5 1.5

DS21Qx5y

.33 .01 .33

VDD VDD

DS21Qx5y

68

.01

.33 .33

68

DS21Qx5y

DS21Q354N

DS21Q354N

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