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DS21Q354N

P1-P3P4-P6P7-P9P10-P12P13-P13
DALLAS SEMICONDUCTOR DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
December 29, 1998 7
A17 DVSS2 – Digital Signal Ground.
A20 DVSS2 – Digital Signal Ground.
B11 DVSS2 – Digital Signal Ground.
C13 DVSS2 – Digital Signal Ground.
A5 DVSS3 – Digital Signal Ground.
B7 DVSS3 – Digital Signal Ground.
B9 DVSS3 – Digital Signal Ground.
C3 DVSS3 – Digital Signal Ground.
H20 DVSS4 – Digital Signal Ground
L20 DVSS4 – Digital Signal Ground
N17 DVSS4 – Digital Signal Ground
U13 DVSS4 – Digital Signal Ground
U1 INT* O Interrupt for all four SCTs.
Y15 JTCLK I JTAG Clock.
N1 JTDI I JTAG Data Input.
H18 JTDO2 O JTAG Data Output from SCT2.
V17 JTDO3 O JTAG Data Output from SCT3.
V19 JTDO4 O JTAG Data Output from SCT4.
W13 JTMS I JTAG Test Mode Select.
V18 JTRST* I JTAG Reset.
K2 LIUC I Line Interface Connect for all Four SCTs.
T1 MCLK1 I Master Clock for SCT1 and SCT3.
W20 MCLK2 I Master Clock for SCT2 and SCT4.
U10 MUX I Mux Bus Select.
M2 RCHBLK1 O Receive Channel Block for SCT1.
G17 RCHBLK2 O Receive Channel Block for SCT2.
G4 RCHBLK3 O Receive Channel Block for SCT3.
Y12 RCHBLK4 O Receive Channel Block for SCT4.
J1 RCHCLK1 O Receive Channel Clock for SCT1.
D14 RCHCLK2 O Receive Channel Clock for SCT2.
F3 RCHCLK3 O Receive Channel Clock for SCT3.
U14 RCHCLK4 O Receive Channel Clock for SCT4.
N3 RCLK1 O Receive Clock Output from the Framer on SCT1.
B13 RCLK2 O Receive Clock Output from the Framer on SCT2.
E3 RCLK3 O Receive Clock Output from the Framer on SCT3.
M18 RCLK4 O Receive Clock Output from the Framer on SCT4.
M4 RCLKI1 I Receive Clock Input for the LIU on SCT1.
A15 RCLKI2 I Receive Clock Input for the LIU on SCT2.
A4 RCLKI3 I Receive Clock Input for the LIU on SCT3.
R17 RCLKI4 I Receive Clock Input for the LIU on SCT4.
M3 RCLKO1 O Receive Clock Output from the LIU on SCT1.
C14 RCLKO2 O Receive Clock Output from the LIU on SCT2.
B4 RCLKO3 O Receive Clock Output from the LIU on SCT3.
T17 RCLKO4 O Receive Clock Output from the LIU on SCT4.
N2 RD*(DS*) I Read Input (Data Strobe)
K4 RFSYNC1 O Receive Frame Sync (before the receive elastic store) for SCT1.
D17 RFSYNC2 O Receive Frame Sync (before the receive elastic store) for SCT2.
A2 RFSYNC3 O Receive Frame Sync (before the receive elastic store) for SCT3.
V14 RFSYNC4 O Receive Frame Sync (before the receive elastic store) for SCT4.
F1 RLCLK1 O Receive Link Clock for SCT1.
A12 RLCLK2 O Receive Link Clock for SCT2.
D3 RLCLK3 O Receive Link Clock for SCT3.
K18 RLCLK4 O Receive Link Clock for SCT4.
G2 RLINK1 O Receive Link Data for SCT1.
A13 RLINK2 O Receive Link Data for SCT2.
A3 RLINK3 O Receive Link Data for SCT3.
U12 RLINK4 O Receive Link Data for SCT4.
DALLAS SEMICONDUCTOR DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
December 29, 1998 8
H2 RLOS/LOTC1 O Receive Loss Of Sync / Loss Of Transmit Clock for SCT1.
E17 RLOS/LOTC2 O Receive Loss Of Sync / Loss Of Transmit Clock for SCT2.
E1 RLOS/LOTC3 O Receive Loss Of Sync / Loss Of Transmit Clock for SCT3.
V11 RLOS/LOTC4 O Receive Loss Of Sync / Loss Of Transmit Clock for SCT4.
L1 RMSYNC1 O Receive Multiframe Sync for SCT1.
D16 RMSYNC2 O Receive Multiframe Sync for SCT2.
F2 RMSYNC3 O Receive Multiframe Sync for SCT3.
W16 RMSYNC4 O Receive Multiframe Sync for SCT4.
R3 RNEGI1 I Receive Negative Data for the Framer on SCT1.
D13 RNEGI2 I Receive Negative Data for the Framer on SCT2.
A1 RNEGI3 I Receive Negative Data for the Framer on SCT3.
P17 RNEGI4 I Receive Negative Data for the Framer on SCT4.
L3 RNEGO1 O Receive Negative Data from the LIU on SCT1.
B15 RNEGO2 O Receive Negative Data from the LIU on SCT2.
C2 RNEGO3 O Receive Negative Data from the LIU on SCT3.
U17 RNEGO4 O Receive Negative Data from the LIU on SCT4.
R4 RPOSI1 I Receive Positive Data for the Framer on SCT1.
B14 RPOSI2 I Receive Positive Data for the Framer on SCT2.
B2 RPOSI3 I Receive Positive Data for the Framer on SCT3.
V15 RPOSI4 I Receive Positive Data for the Framer on SCT4.
L4 RPOSO1 O Receive Positive Data from the LIU on SCT1.
A16 RPOSO2 O Receive Positive Data from the LIU on SCT2.
B1 RPOSO3 O Receive Positive Data from the LIU on SCT3.
U15 RPOSO4 O Receive Positive Data from the LIU on SCT4.
Y11 RRING1 I Receive Analog Ring Input for SCT1.
Y14 RRING2 I Receive Analog Ring Input for SCT2.
Y17 RRING3 I Receive Analog Ring Input for SCT3.
Y20 RRING4 I Receive Analog Ring Input for SCT4.
J2 RSER1 O Receive Serial Data for SCT1.
D15 RSER2 O Receive Serial Data for SCT2.
E2 RSER3 O Receive Serial Data for SCT3.
W17 RSER4 O Receive Serial Data for SCT4.
L2 RSIG1 O Receive Signaling Output for SCT1.
B16 RSIG2 O Receive Signaling Output for SCT2.
C1 RSIG3 O Receive Signaling Output for SCT3.
Y18 RSIG4 O Receive Signaling Output for SCT4.
K1 RSIGF1 O Receive Signaling Freeze Output for SCT1.
C15 RSIGF2 O Receive Signaling Freeze Output for SCT2.
D2 RSIGF3 O Receive Signaling Freeze Output for SCT3.
V16 RSIGF4 O Receive Signaling Freeze Output for SCT4.
G1 RSYNC1 I/O Receive Sync for SCT1.
D12 RSYNC2 I/O Receive Sync for SCT2.
D1 RSYNC3 I/O Receive Sync for SCT3.
V12 RSYNC4 I/O Receive Sync for SCT4.
H1 RSYSCLK1 I Receive System Clock for SCT1.
F17 RSYSCLK2 I Receive System Clock for SCT2.
G3 RSYSCLK3 I Receive System Clock for SCT3.
W14 RSYSCLK4 I Receive System Clock for SCT4.
Y10 RTIP1 I Receive Analog Tip Input for SCT1.
Y13 RTIP2 I Receive Analog Tip Input for SCT2.
Y16 RTIP3 I Receive Analog Tip Input for SCT3.
Y19 RTIP4 I Receive Analog Tip Input for SCT4.
P1 RVDD1 – Receive Analog Positive Supply.
J17 RVDD2 – Receive Analog Positive Supply.
E4 RVDD3 – Receive Analog Positive Supply.
W18 RVDD4 – Receive Analog Positive Supply.
R2 RVSS1 – Receive Analog Signal Ground
DALLAS SEMICONDUCTOR DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
December 29, 1998 9
T2 RVSS1 – Receive Analog Signal Ground
H19 RVSS2 – Receive Analog Signal Ground
J18 RVSS2 – Receive Analog Signal Ground
D4 RVSS3 – Receive Analog Signal Ground
D5 RVSS3 – Receive Analog Signal Ground
V20 RVSS4 – Receive Analog Signal Ground
W19 RVSS4 – Receive Analog Signal Ground
W1 TCHBLK1 O Transmit Channel Block for SCT1.
F20 TCHBLK2 O Transmit Channel Block for SCT2.
C11 TCHBLK3 O Transmit Channel Block for SCT3.
U20 TCHBLK4 O Transmit Channel Block for SCT4.
V10 TCHCLK1 O Transmit Channel Clock for SCT1.
A18 TCHCLK2 O Transmit Channel Clock for SCT2.
B8 TCHCLK3 O Transmit Channel Clock for SCT3.
L18 TCHCLK4 O Transmit Channel Clock for SCT4.
Y9 TCLK1 I Transmit Clock for SCT1.
B19 TCLK2 I Transmit Clock for SCT2.
B10 TCLK3 I Transmit Clock for SCT3.
M19 TCLK4 I Transmit Clock for SCT4.
V6 TCLKI1 I Transmit Clock Input for the LIU on SCT1.
D19 TCLKI2 I Transmit Clock Input for the LIU on SCT2.
C8 TCLKI3 I Transmit Clock Input for the LIU on SCT3.
P20 TCLKI4 I Transmit Clock Input for the LIU on SCT4.
W7 TCLKO1 O Transmit Clock Output from the Framer on SCT1.
E18 TCLKO2 O Transmit Clock Output from the Framer on SCT2.
A7 TCLKO3 O Transmit Clock Output from the Framer on SCT3.
P19 TCLKO4 O Transmit Clock Output from the Framer on SCT4.
U16 TEST I Test (0 = normal operation / 1 = tri-state all outputs).
V3 TLCLK1 O Transmit Link Clock for SCT1.
E20 TLCLK2 O Transmit Link Clock for SCT2.
D6 TLCLK3 O Transmit Link Clock for SCT3.
T18 TLCLK4 O Transmit Link Clock for SCT4.
W5 TLINK1 I Transmit Link Data for SCT1.
E19 TLINK2 I Transmit Link Data for SCT2.
C6 TLINK3 I Transmit Link Data for SCT3.
T19 TLINK4 I Transmit Link Data for SCT4.
R1 TNEGI1 I Transmit Negative Data Input for the LIU on SCT1.
F19 TNEGI2 I Transmit Negative Data Input for the LIU on SCT2.
D8 TNEGI3 I Transmit Negative Data Input for the LIU on SCT3.
R20 TNEGI4 I Transmit Negative Data Input for the LIU on SCT4.
T3 TNEGO1 O Transmit Negative Data Output from Framer on SCT1.
B20 TNEGO2 O Transmit Negative Data Output from Framer on SCT2.
D9 TNEGO3 O Transmit Negative Data Output from Framer on SCT3.
N20 TNEGO4 O Transmit Negative Data Output from Framer on SCT4.
W3 TPOSI1 I Transmit Positive Data Input for the LIU on SCT1.
C20 TPOSI2 I Transmit Positive Data Input for the LIU on SCT2.
A8 TPOSI3 I Transmit Positive Data Input for the LIU on SCT3.
R19 TPOSI4 I Transmit Positive Data Input for the LIU on SCT4.
V7 TPOSO1 O Transmit Positive Data Output from Framer on SCT1.
C19 TPOSO2 O Transmit Positive Data Output from Framer on SCT2.
C9 TPOSO3 O Transmit Positive Data Output from Framer on SCT3.
N19 TPOSO4 O Transmit Positive Data Output from Framer on SCT4.
Y2 TRING1 O Transmit Analog Ring Output for SCT1.
Y4 TRING2 O Transmit Analog Ring Output for SCT2.
Y6 TRING3 O Transmit Analog Ring Output for SCT3.
Y8 TRING4 O Transmit Analog Ring Output for SCT4.
W9 TSER1 I Transmit Serial Data for SCT1.
P1-P3P4-P6P7-P9P10-P12P13-P13

DS21Q354N

Mfr. #:
Buy DS21Q354N
Manufacturer:
Maxim Integrated
Description:
IC TXRX T1/E1 QD 3.3V IND 256BGA
Lifecycle:
New from this manufacturer.
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