1VDDR PWR
3.3V power for differential input clock (receiver). This VDD should be treated as an
analog power rail and filtered appropriately.
2 SRC_IN IN 0.7 V Differential SRC TRUE input
3 SRC_IN# IN 0.7 V Differential SRC COMPLEMENTARY input
4 GND PWR Ground pin.
5 VDD PWR Power supply, nominal 3.3V
6 DIF_1 OUT 0.7V differential true clock output
7 DIF_1# OUT 0.7V differential Complementary clock output
8OE_1 IN
Active high input for enabling output 1.
0 =disable outputs, 1= enable outputs
9 DIF_2 OUT 0.7V differential true clock output
10 DIF_2# OUT 0.7V differential Complementary clock output
11 VDD PWR Power supply, nominal 3.3V
12 BYPASS#_133_100 IN
Input to select Bypass(fan-out), QPI PLL (133MHz) or PCIe PLL (100MHz) mode
0 = Bypass mode, M= QPI, 1= PCIe PLL mode
13 SCLK IN Clock pin of SMBus circuitry, 5V tolerant.
14 SDATA I/O Data pin for SMBus circuitry, 5V tolerant.
15 PD# IN
Asynchronous active low input pin used to power down the device. The internal
clocks are disabled and the VCO and the crystal osc. (if any) are stopped.
16 DIF_STOP# IN Active low input to stop differential output clocks.
17 HIGH_BW# IN
3.3V input for selecting PLL Band Width
0 = High, 1= Low
18 VDD PWR Power supply, nominal 3.3V
19 DIF_5# OUT 0.7V differential Complementary clock output
20 DIF_5 OUT 0.7V differential true clock output
21 OE_6 IN
Active high input for enabling output 6.
0 =disable outputs, 1= enable outputs
22 DIF_6# OUT 0.7V differential Complementary clock output
23 DIF_6 OUT 0.7V differential true clock output
24 VDD PWR Power supply, nominal 3.3V
25 OE_INV IN
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
26 IREF OUT
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the standard value for
