ICS9DB423B
4-OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2, AND QPI
IDT®
4-OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2, AND QPI 10
ICS9DB423B REV E 091812
Vdiff Vp-p Vcm R1 R2 R3 R4 Note
0.45v 0.22v 1.08 33 150 100 100
0.58 0.28 0.6 33 78.7 137 100
0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible
0.60 0.3 1.2 33 174 140 100 Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Alternative Termination for LVDS and other Common Differential Signals (figure 3)
HCSL Output Buffer
L1
L1'
R1b
L2
L2'
R1a
L4'
L4
L3
R2a R2b
Down Device
REF_CLK Input
Figure 3
L3'
R3 R4
Component Value Note
R5a, R5b 8.2K 5%
R6a, R6b 1K 5%
Cc 0.1 µF
Vcm 0.350 volts
Cable Connected AC Coupled Application (figure 4)
PCIe Device
REF_CLK Input
Figure 4
R5a
L4'
L4
3.3 Volts
R5b
R6a R6b
Cc
Cc
ICS9DB423B
4-OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2, AND QPI
IDT®
4-OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2, AND QPI 11
ICS9DB423B REV E 091812
General SMBus Serial Interface Information
How to Write
Controller (host) sends a start bit
Controller (host) sends the write address DC
(h)
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read
Controller (host) will send a start bit
Controller (host) sends the write address DC
(h)
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address DD
(h)
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X
(H)
was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
DC
(h)
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
O O
O O
O
Byte N + X - 1
ACK
PstoP bit
Read Address Write Address
DD
(h)
DC
(h)
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
DC
(h)
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
DD
(h)
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
O O
O O
O
Byte N + X - 1
N Not acknowledge
PstoP bit
ICS9DB423B
4-OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2, AND QPI
IDT®
4-OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2, AND QPI 12
ICS9DB423B REV E 091812
SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD)
Pin # Name Control Function T
yp
e0 1Defaul
t
Bit 7
PD_Mode PD# drive mode RW driven Hi-Z 0
Bit 6
STOP_Mode DIF_Stop# drive mode RW driven Hi-Z 0
Bit 5
PD_Polarity Select PD polarity RW Lo
w
High 0
Bit 4
X
Bit 3
BYPASS#1 BYPASS#/PLL1 RW Input
Bit 2
PLL_BW# Select PLL BW RW High BW Low BW 1
Bit 1
BYPASS#0 BYPASS#/PLL0 RW Input
Bit 0
SRC_DIV# SRC Divide by 2 Select RW x/2 x/1 1
SMBus Table: Output Control Register
Pin # Name Control Function T
yp
e0 1Defaul
t
Bit 7
1
Bit 6
DIF_6 Output Enable RW Disable Enable 1
Bit 5
DIF_5 Output Enable RW Disable Enable 1
Bit 4
1
Bit 3
1
Bit 2
DIF_2 Output Enable RW Disable Enable 1
Bit 1
DIF_1 Output Enable RW Disable Enable 1
Bit 0
1
NOTE:
The SMBus Output Enable Bit must be '1' AND the respective OE pin must be active for the output to run!
SMBus Table: OE Pin Control Register
Pin # Name Control Function T
yp
e0 1Defaul
t
Bit 7
0
Bit 6
DIF_6 DIF_6 Stoppable with DIFSTOP RW Free-run Stoppable 0
Bit 5
DIF_5 DIF_5 Stoppable with DIFSTOP RW Free-run Stoppable 0
Bit 4
0
Bit 3
0
Bit 2
DIF_2 DIF_2 Stoppable with DIFSTOP RW Free-run Stoppable 0
Bit 1
DIF_1 DIF_1 Stoppable with DIFSTOP RW Free-run Stoppable 0
Bit 0
0
SMBus Table: Reserved Register
Pin # Name Control Function T
yp
e0 1Defaul
t
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
B
y
te 3
B
y
te 2
Reserved
19,20
9,10
6,7
22,23
B
y
te 1
22,23
19,20
9,10
6,7
B
y
te 0
-
-
-
-
-
-
-
-
See Bypass Readback
Table
See Bypass Readback
Table
Reserved

9DB423BFLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 4 OUTPUT PCIE GEN2 BUFFER w/QPI
Lifecycle:
New from this manufacturer.
Delivery:
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