Rev. Issue Date Description Page #
A 9/30/2008
1. Updated Electrical Characteristics to add propagation delay and phase noise information.
2. Corrected SMBus to reference pin numbers for 423 instead of 823 device.
3. Removed references to OE controls that are not present on 423.
4. Added SMBus electrical characteristics
5. Added foot note about DIF input running in order for the SMBus interface to work
6. Added foot note to Byte 1 about functionality of OE bits and OE pins.
7. Corrected Block Diagram with proper OE pins indicated and PD and DIF_STOP# pins
added
8. Updated clock periods to reflect +/-100ppm input clock tolerance
(CK410B+/CK420BQ/CK505).
9. Changed SRC_Stop references to DIF_Stop references for consistency.
Various
B 2/3/2010
1. Corrected Polarity of PD pin when OE_INV = 1. PD is always active low (or PD#). This is
a difference from the 9DB803D.
Various
C 1/27/2011 Updated Termination Figure 4 10
D 5/9/2011
1. Update pin 1 pin-name and pin description from VDD to VDDR. This highlights that
optimal peformance is obtained by treating VDDR as in analog pin. This is a document
update only, there is no silicon change.
Various
E 9/18/2012
1. Updated Byte 2, bits 1, 2, 5 and 6 per char review. Outputs can be programmed with Byte
2 to be Stoppable or Free-Run with DIF_Stop pin, not the OE pins.
2. Re-created datasheet in FrameMaker.
Various
