®
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz, with
voltage regulator
Rev. 03 — 2 July 2012 Product data sheet
1. General description
The ADC1003S030/040/050 are a family of 10-bit high-speed low-power Analog-to-Digital
Converters (ADC) for professional video and other applications. They convert the analog
input signal into 10-bit binary-coded digital words at a maximum sampling rate of 50 MHz.
All digital inputs and outputs are Transistor-Transistor Logic (TTL) and CMOS compatible,
although a low-level sine wave clock input signal is allowed.
The device includes an internal voltage reference
regulator. If the application requires that
the reference is driven via external sources the recommendation is to use one of the
ADC1004S030/040/050 family.
2. Features
10-bit resolution
Sa
mpling rate up to 50 MHz
DC sampling allowed
One
clock cycle conversion only
High
signal-to-noise ratio over a large analog input frequency range
(9.3 effective bits at 4.43 MHz full-scale input at f
clk
= 40 MHz)
No missing cod
es guaranteed
In-R
ange (IR) CMOS output
L
evels TTL and CMOS compatible digital inputs
3
V to 5 V CMOS digital outputs
Low-lev
el AC clock input signal allowed
In
ternal reference voltage regulator
Powe
r dissipation only 235 mW (typical)
L
ow analog input capacitance, no buffer amplifier required
No samp
le-and-hold circuit required
3. Applications
High-speed analog-to-digital conversion for:
V
ideo data digitizing
Radar
T
ransient signal analysis
Global Pos
itioning System (GPS) receiver
 m
odulators
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 2 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
Cellular based stations
Bar
code scanner
Medical imaging
4. Quick reference data
Table 1. Quick reference data
V
CCA
= V3 to V4 = 4.75 V to 5.25 V; V
CCD
= V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
V
CCO
= V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; T
amb
= 0
C to 70
C;
typical values measured at V
CCA
= V
CCD
= 5 V and V
CCO
= 3.3 V; C
L
= 15 pF and T
amb
= 25

C;
unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V
CCA
analog supply voltage 4.75 5.0 5.25 V
V
CCD
digital supply voltage 4.75 5.0 5.25 V
V
CCO
output supply voltage 3.0 3.3 5.25 V
I
CCA
analog supply current - 30 35 mA
I
CCD
digital supply current - 16 21 mA
I
CCO
output supply current f
clk
= 40 MHz;
ramp input
- 1 2 mA
INL integral non-linearity f
clk
= 40 MHz;
ramp input
- 0.8 2.0 LSB
DNL differential non-linearity f
clk
= 40 MHz;
ramp input
- 0.5 0.9 LSB
f
clk(max)
maximum clock
frequency
ADC1003S030TS 30 - - MHz
ADC1003S040TS 40 - - MHz
ADC1003S050TS 50 - - MHz
P
tot
total power dissipation f
clk
= 40 MHz;
ramp input
- 235 305 mW
5. Ordering information
Table 2. Ordering information
Type number Package Sampling
frequency
(MHz)
Name Description Version
ADC1003S030TS SSOP28 plastic shrink small outline package; 28 leads;
body width 5.3 mm
SOT341-1 30
ADC1003S040TS SSOP28 plastic shrink small outline package; 28 leads;
body width 5.3 mm
SOT341-1 40
ADC1003S050TS SSOP28 plastic shrink small outline package; 28 leads;
body width 5.3 mm
SOT341-1 50
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 3 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
6. Block diagram
12
DGND2
6
8
R
lad
7
9
RB
RM
RT
VI
11
V
CCD2
35
26
V
CCA
21
22
23
24
20 D4
D5
D6
D7
D8
19
18
25
2
D3
D2
17 D1
16 D0
D9
IN-RANGE LATCH
CMOS
OUTPUTS
LATCHES
CLOCK DRIVER
REFERENCE
VOLTAGE
REGULATOR
014aaa321
1
CLKDEC
10
OE
TC
ADC1003S030/040/050
13
V
CCO
4
AGND
analog ground digital ground digital ground
27
DGND1
14
OGND
output ground
analog
voltage input
data outputs
LSB
MSB
28
V
CCD1
IR
output
CMOS OUTPUT
ANALOG - TO - DIGITAL
CONVERTER
Fig 1. Block diagram

ADC1003S030TS/C1,1

Mfr. #:
Manufacturer:
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Lifecycle:
New from this manufacturer.
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