ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 9 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
[1] In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less
than 0.5 ns
[2] Analog input voltages producing code 0 up to and including code 1023:
a) V
offset
BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB
(V
RB
) at T
amb
= 25 C.
b) V
offset
TOP is the difference between reference voltage on pin RT (V
RT
) and the analog input which produces data outputs equal to
code 1023 at T
amb
= 25 C.
[3] In order to ensure the optimum linearity performance of such converter
architecture the lower and upper extremities of the converter
reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins RB and RT via offset resistors
R
OB
and R
OT
as shown in Figure 3.
a) The current flowing into the resistor ladder is
I
L
V
RT
V
RB
–
R
OB
R
L
R
OT
++
---------------------------------------
=
and the full-scale input range at the converter
to cover code 0 to code 1023, is
V
I
R
L
I
L
R
L
R
OB
R
L
R
OT
++
---------------------------------------
V
RT
V
RB
– 0.848 V
RT
V
RB
–== =
b) Since R
L
, R
OB
and R
OT
have similar behavior with respect to process and temperature variation, the ratio
R
L
R
OB
R
L
R
OT
++
---------------------------------------
will
be kept reasonably constant from device to device. Co
nsequently, variation of the output codes at a given input voltage depends
mainly on the difference V
RT
V
RB
and its variation with temperature and supply voltage. When several ADCs are connected in
parallel and fed with the same reference source, the matching between each of them is optimized.
[4]
E
G
V
1023
V
0
–V
i PP–
–
V
i PP–
--------------------------------------------------------
100=
[5] The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater
than 2 LSB, neither any significant attenuation are observed in the reconstructed signal.
[6] The analog input settling time is the minimum time required
for the input signal to be stabilized after a sharp full-scale input (square
wave signal) in order to sample the signal and obtain correct output data.
Differential phase
[9]
dif
differential phase f
clk
= 40 MHz;
PAL modulated ramp
- 0.4 - deg
Timing (f
clk
= 40 MHz; C
L
= 15 pF); see Figure 4
[10]
t
d(s)
sampling delay time - 3 - ns
t
h(o)
output hold time 4 - - ns
t
d(o)
output delay time V
CCO
= 4.75 V - 10 13 ns
V
CCO
= 3.15 V - 12 15 ns
C
L
load capacitance - - 15 pF
3-state output delay times; see Figure 5
t
dZH
float to active HIGH delay
time
- 5.5 8.5 ns
t
dZL
float to active LOW delay
time
- 12 15 ns
t
dHZ
active HIGH to float delay
time
- 19 24 ns
t
dLZ
active LOW to float delay
time
- 12 15 ns
Table 6. Characteristics …continued
V
CCA
= V3 to V4 = 4.75 V to 5.25 V; V
CCD
= V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
V
CCO
= V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; T
amb
= 0
C to 70
C; typical values measured at
V
CCA
= V
CCD
= 5 V and V
CCO
= 3.3 V; C
L
= 15 pF and T
amb
= 25
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
