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ADC1003S030TS/C1,1

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ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 4 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
7. Pinning information
7.1 Pinning
ADC1003S
050TS
CLK
V
CCD1
TC DGND1
V
CCA
IR
AGND D9
DEC D8
RB D7
RM D6
VI D5
RT D4
OE D3
V
CCD2
D2
DGND2 D1
V
CCO
D0
OGND n.c.
014aaa320
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
18
17
20
19
22
21
24
23
26
25
28
27
Fig 2. Pin configuration
7.2 Pin description
Table 3. Pin description
Symbol Pin Description
CLK 1 clock input
TC 2 two’s complement input (active LOW)
V
CCA
3 analog supply voltage (5 V)
AGND 4 analog ground
DEC 5 decoupling input
RB 6 reference voltage BOTTOM input
RM 7 reference voltage MIDDLE
VI 8 analog input voltage
RT 9 reference voltage TOP input
OE 10 output enable input (CMOS level input, active LOW)
V
CCD2
11 digital supply voltage 2 (5 V)
DGND2 12 digital ground 2
V
CCO
13 supply voltage for output stages (3 V to 5 V)
OGND 14 output ground
n.c. 15 not connected
D0 16 data output; bit 0 (Least Significant Bit (LSB))
D1 17 data output; bit 1
D2 18 data output; bit 2
D3 19 data output; bit 3
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 5 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
CCA
analog supply voltage
[1]
0.3 +7.0 V
V
CCD
digital supply voltage
[1]
0.3 +7.0 V
V
CCO
output supply voltage staged
[1]
0.3 +7.0 V
V
CC
supply voltage difference V
CCA
V
CCD
1.0 +1.0 V
V
CCA
V
CCO
1.0 +4.0 V
V
CCD
V
CCO
1.0 +4.0 V
V
I
input voltage referenced to
AGND
0.3 +7.0 V
V
i(clk)(p-p)
peak-to-peak clock input
voltage
referenced to
DGND
- V
CCD
V
I
O
output current - 10 mA
T
stg
storage temperature 55 +150 C
T
amb
ambient temperature 40 +85 C
T
j
junction temperature - 150 C
[1] The supply voltages V
CCA
, V
CCD
and V
CCO
may have any value between 0.3 V and +7.0 V provided that
the supply voltage differences V
CC
are respected.
9. Thermal characteristics
Table 5. Thermal characteristics
Symbol Parameter Conditions Typ Unit
R
th(j-a)
thermal resistance from junction
to ambient
in free air 110 K/W
D4 20 data output; bit 4
D5 21 data output; bit 5
D6 22 data output; bit 6
D7 23 data output; bit 7
D8 24 data output; bit 8
D9 25 data output; bit 9 (Most Significant Bit (MSB))
IR 26 in-range data output
DGND1 27 digital ground 1
V
CCD1
28 digital supply voltage 1 (5 V)
Table 3. Pin description …continued
Symbol Pin Description
ADC1003S030_040_050_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 6 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
10. Characteristics
Table 6. Characteristics
V
CCA
= V3 to V4 = 4.75 V to 5.25 V; V
CCD
= V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
V
CCO
= V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; T
amb
= 0
C to 70
C; typical values measured at
V
CCA
= V
CCD
= 5 V and V
CCO
= 3.3 V; C
L
= 15 pF and T
amb
= 25

C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
V
CCA
analog supply voltage 4.75 5.0 5.25 V
V
CCD
digital supply voltage 4.75 5.0 5.25 V
V
CCO
output supply voltage 3.0 3.3 5.25 V
V
CC
supply voltage difference V
CCA
V
CCD
0.2 - +0.20 V
V
CCA
V
CCO
0.2 - +2.25 V
V
CCA
V
CCO
0.2 - +2.25 V
I
CCA
analog supply current - 30 35 mA
I
CCD
digital supply current - 16 21 mA
I
CCO
output supply current f
clk
= 40 MHz;
ramp input
- 1 2 mA
P
tot
total power dissipation f
clk
= 40 MHz;
ramp
input
- 235 305 mW
Inputs
Clock input CLK (referenced to DGND)
[1]
V
IL
LOW-level input voltage 0 - 0.8 V
V
IH
HIGH-level input voltage 2 - V
CCD
V
I
IL
LOW-level input current V
clk
= 0.8 V 1 0 +1 A
I
IH
HIGH-level input current V
clk
= 2 V - 2 10 A
Z
i
input impedance f
clk
= 40 MHz - 2 - k
C
i
input capacitance - 2 - pF
Inputs OE and TC (referenced to DGND)
V
IL
LOW-level input voltage 0 - 0.8 V
V
IH
HIGH-level input voltage 2 - V
CCD
V
I
IL
LOW-level input current V
IL
= 0.8 V 1 - - A
I
IH
HIGH-level input current V
IH
= 2 V - - 1 A
VI (Analog input voltage referenced to AGND)
I
IL
LOW-level input current V
I
= V
RB
= 1.3 V - 0 - A
I
IH
HIGH-level input current V
I
= V
RT
= 3.67 V - 35 - A
Z
i
input impedance f
i
= 4.43 MHz - 8 - k
C
i
input capacitance - 5 - pF
Reference voltages for the resistor ladder using the internal voltage regulator see Table 7
V
RB
voltage on pin RB 1.1 1.3 1.5 V
V
RT
voltage on pin RT 3.4 3.6 3.8 V
V
ref(dif)
differential reference
voltage
V
RT
V
RB
2.25 2.3 2.35 V
I
ref
reference current - 9.39 - mA
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ADC1003S030TS/C1,1

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