P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 59 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
The device exits Idle mode through either a system interrupt or a hardware reset. When
exiting Idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits
Idle mode. After exiting the Interrupt Service Routine, the interrupted program resumes
execution beginning at the instruction immediately following the instruction which invoked
the Idle mode. A hardware reset starts the device similar to a power-on reset.
6.12.2 Power-down mode
The Power-down mode is entered by setting the PD bit in the PCON register. In the
Power-down mode, the clock is stopped and external interrupts are active for level
sensitive interrupts only. SRAM contents are retained during Power-down mode, and the
minimum V
DD
level is 2.0 V.
The device exits Power-down mode through either an enabled external level sensitive
interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits
Power-down. Holding the external interrupt pin low restarts the oscillator, the signal must
hold low at least 1024 clock cycles before bringing back high to complete the exit. Upon
interrupt signal restored to logic V
IH
, the interrupt service routine program execution
resumes beginning at the instruction immediately following the instruction which invoked
Power-down mode. A hardware reset starts the device similar to power-on reset.
To exit properly out of Power-down mode, the reset or external interrupt should not be
executed before the V
DD
line is restored to its normal operating voltage. Be sure to hold
V
DD
voltage long enough at its normal operating level for the oscillator to restart and
stabilize (normally less than 10 ms).
Table 56. Power-saving modes
Mode Initiated by State of MCU Exited by
Idle mode Software (Set IDL bit in
PCON) MOV PCON, #01H
Clock is running. Interrupts,
serial port and timers/counters
are active. Program Counter is
stopped. ALE and
PSEN
signals are HIGH level during
Idle. All registers remain
unchanged.
Enabled interrupt or hardware reset. Start of
interrupt clears IDL bit and exits Idle mode,
after the ISR (Interrupt Service Routine)
RETI (Return from Interrupt) instruction,
program resumes execution beginning at
the instruction following the one that invoked
Idle mode. A user could consider placing
two or three NOP (No Operation)
instructions after the instruction that invokes
Idle mode to eliminate any problems. A
hardware reset restarts the device similar to
a power-on reset.
Power-down
mode
Software (Set PD bit in
PCON) MOV PCON, #02H
Clock is stopped. On-chip
SRAM and SFR data is
maintained. ALE and
PSEN
signals are LOW level during
power-down. External
Interrupts are only active for
level sensitive interrupts, if
enabled.
Enabled external level sensitive interrupt or
hardware reset. Start of interrupt clears PD
bit and exits Power-down mode, after the
ISR RETI instruction program resumes
execution beginning at the instruction
following the one that invoked Power-down
mode. A user could consider placing two or
three NOP instructions after the instruction
that invokes Power-down mode to eliminate
any problems. A hardware reset restarts the
device similar to a power-on reset.